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november 1990 80C196KB user's guide order number: 270651-003
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80C196KB user's guide contents page 1.0 cpu operation 1 1.1 memory controller 2 1.2 cpu control 2 1.3 internal timing 2 2.0 memory space 4 2.1 register file 4 2.2 special function registers 4 2.3 reserved memory spaces 8 2.4 internal rom and eprom 8 2.5 system bus 9 3.0 software overview 9 3.1 operand types 9 3.2 operand addressing 10 3.3 program status word 12 3.4 instruction set 14 3.5 80C196KB instruction set additions and differences 22 3.6 software standards and conventions 22 3.7 software protection hints 23 4.0 peripheral overview 23 4.1 pulse width modulation output (d/a) 24 4.2 timers 24 4.3 high speed inputs (hsi) 24 4.4 high speed outputs (hso) 24 4.5 serial port 24 4.6 a/d converter 26 4.7 i/o ports 26 4.8 watchdog timer 26 5.0 interrupts 27 5.1 interrupt control 29 5.2 interrupt priorities 29 5.3 critical regions 31 5.4 interrupt timing 31 5.5 interrupt summary 32 contents page 6.0 pulse width modulation output (d/a) 33 6.1 analog outputs 35 7.0 timers 36 7.1 timer1 36 7.2 timer2 36 7.3 sampling on external timer pins 36 7.4 timer interrupts 37 8.0 high speed inputs 38 8.1 hsi modes 39 8.2 hsi status 39 8.3 hsi interrupts 40 8.4 hsi input sampling 40 8.5 initializing the hsi 40 9.0 high speed outputs 40 9.1 hso interrupts and software timers 41 9.2 hso cam 42 9.3 hso status 43 9.4 clearing the hso and locked entries 43 9.5 hso precautions 44 9.6 pwm using the hso 44 9.7 hso output timing 45 10.0 serial port 45 10.1 serial port status and control 47 10.2 serial port interrupts 49 10.3 serial port modes 49 10.4 multiprocessor communications 51 11.0 a/d converter 51 11.1 a/d conversion process 53 11.2 a/d interface suggestions 53 11.3 the a/d transfer function 54 11.4 a/d glossary of terms 58
80C196KB user's guide contents page 12.0 i/o ports 60 12.1 input ports 60 12.2 quasi-bidirectional ports 60 12.3 output ports 62 12.4 ports 3 and 4/ad0 15 63 13.0 minimum hardware considerations 64 13.1 power supply 64 13.2 noise protection tips 64 13.3 oscillator and internal timings 64 13.4 reset and reset status 65 13.5 minimum hardware connections 68 14.0 special modes of operation 69 14.1 idle mode 69 14.2 powerdown mode 69 14.3 once and test modes 70 contents page 15.0 external memory interfacing 71 15.1 bus operation 71 15.2 chip configuration register 72 15.3 bus width 75 15.4 hold /hlda protocol 76 15.5 ac timing explanations 78 15.6 memory system examples 83 15.7 i/o port reconstruction 85 16.0 using the eprom 85 16.1 power-up and power-down 85 16.2 reserved locations 86 16.3 programming pulse width register (ppw) 87 16.4 auto configuration byte programming mode 88 16.5 auto programming mode 88 16.6 slave programming mode 90 16.7 run-time programming 92 16.8 rom/eprom memory protection options 93 16.9 algorithms 94
80C196KB user's guide the 80C196KB family is a chmos branch of the mcs -96 family. other members of the mcs-96 fami- ly include the 8096bh and 8098. all of the mcs-96 components share a common instruction set and archi- tecture. however the chmos components have en- hancements to provide higher performance at lower power consumptions. to further decrease power usage, these parts can be placed into idle and powerdown modes. mcs-96 family members are all high-performance mi- crocontrollers with a 16-bit cpu and at least 230 bytes of on-chip ram. they are register-to-register ma- chines, so no accumulator is needed, and most opera- tions can be quickly performed from or to any of the registers. in addition, the register operations can con- trol the many peripherals which are available on the chips. these peripherals include a serial port, a/d con- verter, pwm output, up to 48 i/o lines and a high- speed i/o subsystem which has 2 16-bit timer/coun- ters, an 8-level input capture fifo and an 8-entry pro- grammable output generator. typical applications for mcs-96 products are closed- loop control and mid-range digital signal processing. mcs-96 products are being used in modems, motor controls, printers, engine controls, photocopiers, anti- lock brakes, air conditioner temperature controls, disk drives, and medical instrumentation. there are many members of the 80C196KB family, so to provide easier reading this manual will refer to the 80C196KB family generically as the 80C196KB. where information applies only to specific components it will be clearly indicated. the 80C196KB can be separated into four sections for the purpose of describing its operation. a block dia- gram is shown in figure 1-1. there is the cpu and architecture, the instruction set, the peripherals and the bus unit. each of the sections will be sub-divided as the discussion progresses. let us first examine the cpu. 1.0 cpu operation the major components of the cpu on the 80C196KB are the register file and the register/arithmetic log- ic unit (ralu). communication with the outside world is done through either the special function reg- isters (sfrs) or the memory controller. the ralu does not use an accumulator. instead, it operates di- rectly on the 256-byte register space made up of the register file and the sfrs. efficient i/o operations are possible by directly controlling the i/o through the sfrs. the main benefits of this structure are the ability to quickly change context, absence of accumulator bot- tleneck, and fast throughput and i/o times. 270651 1 figure 1-1. 80C196KB block diagram 1
80C196KB user's guide the cpu on the 80C196KB is 16 bits wide and con- nects to the interrupt controller and the memory con- troller by a 16-bit bus. in addition, there is an 8-bit bus which transfers instruction bytes from the memory con- troller to the cpu. an extension of the 16-bit bus con- nects the cpu to the peripheral devices. 1.1 memory controller the ralu talks to the memory, except for the loca- tions in the register file and sfr space, through the memory controller. within the memory controller is a bus controller, a four byte queue and a slave program counter (slave pc). both the internal rom/eprom bus and the external memory bus are driven by the bus controller. memory access requests to the bus control- ler can come from either the ralu or the queue, with queue accesses having priority. requests from the queue are always for instruction at the address in the slave pc. by having program fetches from memory referenced to the slave pc, the processor saves time as addresses sel- dom have to be sent to the memory controller. if the address sequence changes because of a jump, interrupt, call or return, the slave pc is loaded with a new value, the queue is flushed, and processing continues. execution speed is increased by using a queue since it usually keeps the next instruction byte available. the instruction execution times shown in section 3 show the normal execution times with no wait states added and the 16-bit bus selected. reloading the slave pc and fetching the first byte of the new instruction stream takes 4 state times. this is reflected in the jump taken/ not-taken times shown in the table. when debugging code using a logic analyzer, one must be aware of the queue. it is not possible to determine when an instruction will begin executing by simply watching when it is fetched, since the queue is filled in advance of instruction execution. 1.2 cpu control a microcode engine controls the cpu, allowing it to perform operations with any byte, word or double word in the 256 byte register space. instructions to the cpu are taken from the queue and stored temporarily in the instruction register. the microcode engine decodes the instructions and generates the correct sequence of events to have the ralu perform the desired function. figure 1-2 shows the memory controller, ralu, in- struction register and the control unit. register/alu (ralu) most calculations performed by the 80C196KB take place in the ralu. the ralu, shown in figure 1-2, contains a 17-bit alu, the program status word (psw), the program counter (pc), a loop counter, and three temporary registers. all of the registers are 16- bits or 17-bits (16 a sign extension) wide. some of the registers have the ability to perform simple operations to off-load the alu. a separate incrementor is used for the program coun- ter (pc) as it accesses operands. however, pc changes due to jumps, calls, returns and interrupts must be han- dled through the alu. two of the temporary registers have their own shift logic. these registers are used for the operations which require logical shifts, including normalize, multiply, and divide. the ``lower word'' and ``upper word'' are used together for the 32-bit instructions and as temporary registers for many in- structions. repetitive shifts are counted by the 6-bit ``loop counter''. a third temporary register stores the second operand of two operand instructions. this includes the multiplier during multiplications and the divisor during divisions. to perform subtractions, the output of this register can be complemented before being placed into the ``b'' in- put of the alu. several constants, such as 0, 1 and 2 are stored in the ralu to speed up certain calculations. (e.g. making a 2's complement number or performing an increment or decrement instruction.) in addition, single bit masks for bit test instructions are generated in the constant regis- ter based on the 3-bit bit select register. 1.3 internal timing the 80C196KB requires an input clock on xtal1 to function. since xtal1 and xtal2 are the input and output of an inverter a crystal can be used to generate the clock. details of the circuit and suggestions for its use can be found in section 13. internal operation of the 80C196KB is based on the crystal or external oscillator frequency divided by 2. every 2 oscillator periods is referred to as one ``state time'', the basic time measurement for all 80C196KB operations. with a 12 mhz oscillator, a state time is 167 nanoseconds. with an 8 mhz oscillator, a state time is 250 nanoseconds, the same as an 8096bh run- ning with a 12 mhz oscillator. since the 80C196KB will be run at many frequencies, the times given throughout this chapter will be in state times or ``states'', unless otherwise specified. a clock out 2
80C196KB user's guide figure 1-2. ralu and memory controller block diagram 270651 2 3
80C196KB user's guide (clkout) signal, shown in figure 1-3, is provided as an indication of the internal machine state. details on timing relationships can be found in section 13. 270651 3 figure 1-3. internal clock waveforms 2.0 memory space the addressable memory space on the 80C196KB con- sists of 64k bytes, most of which is available to the user for program or data memory. locations which have special purposes are 0000h through 00ffh and 1ffeh through 2080h. all other locations can be used for either program or data storage or for memory mapped peripherals. a memory map is shown in figure 2-1. external memory or i/o 0ffffh 4000h internal rom/eprom or external memory * 2080h reserved 2040h upper 8 interrupt vectors (new on 80C196KB) 2030h rom/eprom security key 2020h reserved 2019h chip configuration byte 2018h reserved 2014h lower 8 interrupt vectors plus 2 special interrupts 2000h port 3 and port 4 1ffeh external memory or i/o 0100h internal data memory - register file (stack pointer, ram and sfrs) external program code memory 0000h figure 2-1. 80C196KB memory map 2.1 register file locations 00h through 0ffh contain the register file and special function registers, (sfrs). the ralu can operate on any of these 256 internal register loca- tions, but code can not be executed from them. if an attempt to execute instructions from locations 000h through 0ffh is made, the instructions will be fetched from external memory. this section of external memo- ry is reserved for use by intel development tools the internal ram from location 018h (24 decimal) to 0ffh is the register file. it contains 232 bytes of ram which can be accessed as bytes (8 bits), words (16 bits), or double-words (32 bits). since each of these locations can be used by the ralu, there are essential- ly 232 ``accumulators''. this memory region, as well as the status of the majority of the chip, is kept intact while the chip is in the powerdown mode. details on powerdown mode are discussed in section 14. locations 18h and 19h contain the stack pointer. these are not sfrs and may be used as standard ram if stack operations are not being performed. since the stack pointer is in this area, the ralu can easily oper- ate on it. the stack pointer must be initialized by the user program and can point anywhere in the 64k mem- ory space. operations to the stack cause it to build down, so the stack pointer should be initialized to 2 bytes above the highest stack location, and must be word aligned. 2.2 special function registers locations 00h through 17h are the i/o control regis- ters or sfrs. all of the peripheral devices on the 80C196KB (except ports 3 and 4) are controlled through these registers. as shown in figure 2-2, three sfr windows are provided on the 80C196KB. switching between the windows is done using the win- dow select register (wsr) at location 14h in all of the windows. the pusha and popa instructions push and pop the wsr so it is easy to change between win- dows. only three values may be written to the wsr, 0, 14 and 15. other values are reserved for use in future parts and will cause unpredictable operation. window 0, the register window selected with wsr e 0, is a superset of the one used on the 8096bh. as depict- ed in figure 2-3, it has 24 registers, some of which have different functions when read than when written. reg- isters which are new to the 80C196KB or have changed functions from the 8096 are indicated in the figure. 4
80C196KB user's guide listed registers are present in all three windows 16h 16h 16h 14h wsr 14h wsr 14h wsr 12h int mask1/pend1 12h int mask1/pend1 12h int mask1/pend1 10h 10h 10h 0eh 0eh 0eh 0ch timer2 0ch t2 capture 0ch t2 capture 0ah 0ah 0ah 08h int mask/pend 08h int mask/pend 08h int mask/pend 06h 06h 06h 04h 04h 04h 02h 02h 02h 00h zero reg 00h zero reg 00h zero reg read/write programming write/read wsr e 0 wsr e 14 wsr e 15 figure 2-2. multiple register windows 19h stack pointer 19h stack pointer 18h 18h 17h * ios2 17h pwm e control 16h ios1 16h ioc1 15h ios0 15h ioc0 14h * wsr 14h * wsr 13h * int e mask 1 13h * int e mask 1 12h * int e pend 1 12h * int e pend 1 11h * sp e stat 11h * sp e con 10h port2 10h port2 10h reserved ** 0fh port1 0fh port1 0fh reserved ** 0eh port0 0eh baud rate 0eh reserved ** 0dh timer2 (hi) 0dh timer2 (hi) 0dh * t2 capture (hi) 0ch timer2 (lo) 0ch timer2 (lo) 0ch * t2 capture (lo) 0bh timer1 (hi) 0bh * ioc2 wsr e 15 0ah timer1 (lo) 0ah watchdog 09h int e pend 09h int e pend other sfrs in wsr 15 become 08h int e mask 08h int e mask readable if they were writable 07h sbuf(rx) 07h sbuf(tx) in wsr e 0, and writable if they 06h hsi e status 06h hso e command were readable in wsr e 0 05h hsi e time (hi) 05h hso e time (hi) 04h hsi e time (lo) 04h hso e time (lo) 04h ppw 03h ad e result (hi) 03h hsi e mode wsr e 14 02h ad e result (lo) 02h ad e command 01h zero reg (hi) 01h zero reg (hi) * new or changed register 00h zero reg (lo) 00h zero reg (lo) function from 8096bh when read when written ** reserved registers should not wsr e 0 be written or read figure 2-3. special function registers 5
80C196KB user's guide register description r0 zero register - always reads as a zero, useful for a base when indexing and as a constant for calculations and compares. ad e result a/d result hi/low - low and high order results of the a/d converter ad e command a/d command register - controls the a/d hsi e mode hsi mode register - sets the mode of the high speed input unit. hsi e time hsi time hi/lo - contains the time at which the high speed input unit was triggered. hso e time hso time hi/lo - sets the time or count for the high speed output to execute the command in the command register. hso e command hso command register - determines what will happen at the time loaded into the hso time registers. hsi e status hsi status registers - indicates which hsi pins were detected at the time in the hsi time registers and the current state of the pins. in window 15 - writes to pin detected bits, but not current state bits. sbuf(tx) transmit buffer for the serial port, holds contents to be outputted. last written value is readable in window 15. sbuf(rx) receive buffer for the serial port, holds the byte just received by the serial port. writable in window 15. int e mask interrupt mask register - enables or disables the individual interrupts. int e pend interrupt pending register - indicates that an interrupt signal has occurred on one of the sources and has not been serviced. (also int e pending) watchdog watchdog timer register - written periodically to hold off automatic reset every 64k state times. returns upper byte of wdt counter in window 15. timer1 timer 1 hi/lo - timer1 high and low bytes. timer2 timer 2 hi/lo - timer2 high and low bytes. ioport0 port 0 register - levels on pins of port 0. reserved in window 15. baud e rate register which determines the baud rate, this register is loaded sequentially. reserved in window 15. ioport1 port 1 register - used to read or write to port 1. reserved in window 15 ioport2 port 2 register - used to read or write to port 2. reserved in window 15 sp e stat serial port status - indicates the status of the serial port. sp e con serial port control - used to set the mode of the serial port. ios0 i/o status registe r 0 - contains information on the hso status. writes to hso pins in window 15. ios1 i/o status registe r 1 - contains information on the status of the timers and of the hsi. ioc0 i/o control registe r 0 - controls alternate functions of hsi pins, timer 2 reset sources and timer 2 clock sources. ioc1 i/o control registe r 1 - controls alternate functions of port 2 pins, timer interrupts and hsi interrupts. pwm e control pulse width modulation control register - sets the duration of the pwm pulse. int e pend1 interrupt pending register for the 8 new interrupt vectors (also int e pending1) int e mask1 interrupt mask register for the 8 new interrupt vectors ioc2 i/o control registe r 2 - controls new 80C196KB features ios2 i/o status registe r 2 - contains information on hso events wsr window select register - selects register window figure 2-4. special function register description 6
80C196KB user's guide programming control and test operations are done in window 14. registers in this window that are not la- beled should be considered reserved and should not be either read or written. in register window 15 (wsr e 15), the operation of the sfrs is changed, so that those which were read- only in window 0 space are write-only and vice versa. the only major exception to this is that timer2 is read/ write in window 0, and t2 capture is read/write in window 15. (timer2 was read-only on the 8096.) registers which can be read and written in window 0 can also be read and written in window 15. figure 2-4 contains brief descriptions of the sfr regis- ters. detailed descriptions are contained in the section which discusses the peripheral controlled by the regis- ter. figure 2-5 contains a description of the alternate function in window 15. ad e command (02h) e read the last written command ad e result (02h, 03h) e write a value into the result register hsi e mode (03h) e read the value in hsi e mode hsi e time (04h, 05h) e write to fifo holding register hso e time (04h, 05h) e read the last value placed in the holding register hsi e status (06h) e write to status bits but not to hsi pin bits. (pin bits are 1, 3, 5, 7) hso e command (06h) e read the last value placed in the holding register sbuf(rx) (07h) e write a value into the receive buffer sbuf(tx) (07h) e read the last value written to the transmit buffer watchdog (0ah) e read the value in the upper byte of the wdt timer1 (0ah, 0bh) e write a value to timer1 timer2 (0ch, 0dh) e read/write the timer2 capture register. (timer2 read/write is done with wsr e 0) ioc2 (0bh) e last written value is readable, except bit 7 (note 1) baud e rate (0eh) e no function, cannot be read port0 (0eh) e no function, no output drivers on the pins sp e stat (11h) e set the status bits, ti and ri can be set, but it will not cause an interrupt sp e con (11h) e read the current control byte ios0 (15h) e writing to this register controls the hso pins. bits 6 and 7 are inactive for writes. ioc0 (15h) e last written value is readable, except bit 1 (note 1) ios1 (16h) e writing to this register will set the status bits, but not cause interrupts. bits 6 and 7 are not functional. ioc1 (16h) e last written value is readable ios2 (17h) e writing to this register will set the status bits, but not cause interrupts. pwm e control (17h) e read the duty cycle value written to pwm e control note: 1. ioc2.7 (cam clear) and ioc0.1 (t2rst) are not latched and will read a s a 1 (precharged bus). being able to write to the read-only registers and vice-versa provides a lot of flexibility. one of the most useful advantages is the ability to set the timers and hso lines for initial conditions other than zero. figure 2-5. alternate sfr function in window 15 7
80C196KB user's guide within the sfr space are several registers and bit loca- tions labeled ``reserved''. these locations should never be written or read. a reserved bit location should always be written with 0 to maintain compatibility with future parts. values read from these locations may change from part to part or over temperature and volt- age. registers and bits which are not labeled should be treated as reserved registers and bits. note that the de- fault state of internal registers is 0, while that for exter- nal memory is 1. this is because sfr functions are typically disabled with a zero, while external memory is typically erased to all 1s. caution must be taken when using the sfrs as sources of operations or as base or index registers for indirect or indexed operations. it is possible to get undesired re- sults, since external events can change sfrs and some sfrs clear when read. the potential for an sfr to change value must be taken into account when operat- ing on these registers. this is particularly important when high level languages are used as they may not always make allowances for sfr-type registers. sfrs can be operated on as bytes or words unless otherwise specified. 2.3 reserved memory spaces locations 1ffeh and 1fffh are used for ports 3 and 4 respectively, allowing easy reconstruction of these ports if external memory is used. an example of recon- structing the i/o ports is given in section 15. if ports 3 and 4 are not going to be reconstructed and internal rom/eprom is not used, these locations can be treated as any other external memory location. many reserved and special locations are in the memory area between 2000h and 2080h. in this area the 18 interrupt vectors, chip configuration byte, and security key are located. figure 2-6 shows the locations and functions of these registers. the interrupts, chip config- uration, and security key registers are discussed in sec- tions 5, 16, and 17 respectively. with one exception, all unspecified addresses in locations 2000h through 207fh, including those marked ``reserved'' are re- served by intel for use in testing or future products. they must be filled with the hex value ffh to insure compatibility with future devices. location 2019h should contain 20h to prevent possible bus contention during the ccb fetch cycle. note: 1. this exception applies only to systems with a 16-bit bus and external program memory. 2. previously designed systems which do not experience bus contention don't need to change the contents of this location. refer to section 15.2 for more information about bus contention during ccb fetch. ffffh external memory or i/o 4000h internal program storage rom/eprom or external memory 2080h reserved 2074h207fh voltage levels 2072h2073h signature word 2070h2071h reserved 2040h206fh interrupt vectors 2030h203fh security key 2020h202fh reserved 2019h201fh chip configuration byte 2018h reserved 2015h2017h ppw 2014h interrupt vectors 2000h2013h figure 2-6. reserved memory spaces resetting the 80C196KB causes instructions to be fetched starting from location 2080h. this location was chosen to allow a system to have up to 8k of ram continuous with the register file. further information on reset can be found in section 13. 2.4 internal rom and eprom when a rom part is ordered, or an eprom part is programmed, the internal memory locations 2080h through 3fffh are user specified, as are the interrupt vectors, chip configuration register and security key in locations 2000h through 207fh. location 2014h contains the ppw (programming pulse width) regis- ter. the ppw is used solely to program 87c196kb eprom devices and is a reserved location on rom and romless devices. instruction and data fetches from the internal rom or eprom occur only if the part has rom or eprom, ea is tied high, and the address is between 2000h and 3fffh. at all other times data is accessed from either the internal ram space or external memory and in- structions are fetched from external memory. the ea pin is latched on reset rising. information on pro- gramming eproms can be found in section 16. 8
80C196KB user's guide the 80C196KB provides a rom/eprom lock feature to allow the program to be locked against reading and/or writing the internal program memory. in order to maintain security, code can not be executed out of the last three locations of internal rom/eprom if the lock is enabled. details on this feature are in sec- tion 17. 2.5 system bus there are several modes of system bus operation on the 80C196KB. the standard bus mode uses a 16-bit multi- plexed address/data bus. other bus modes include an 8-bit mode and a mode in which the bus size can dy- namically be switched between 8-bits and 16-bits. hold/hold acknowledge (hold /hlda ) and ready signals are available to create a variety of memory sys- tems. the ready line extends the width of the rd (read) and wr (write) pulses to allow access of slow memories. multiple processor systems with shared memory can be designed using hold /hlda to keep the 80C196KB off the bus. details on the system bus are in section 15. 3.0 software overview this section provides information on writing programs to execute in the 80C196KB. additional information can be found in the following documents: mcs -96 macro assembler user's guide order number 122048 (intel systems) order number 122351 (dos systems) mcs -96 utilities user's guide order number 122049 (intel systems) order number 122356 (dos systems) pl/m-96 user's guide order number 122134 (intel systems) order number 122361 (dos systems) c-96 user's guide order number 167632 (dos systems) throughout this chapter short sections of code are used to illustrate the operation of the device. for these sec- tions it is assumed that the following set of temporary registers has been declared: ax, bx, cx, and dx are 16-bit registers. al is the low byte of ax, ah is the high byte. bl is the low byte of bx cl is the low byte of cx dl is the low byte of dx these are the same as the names for the general data registers used in the 8086. it is important to note that in the 80C196KB these are not dedicated registers but merely the symbolic names assigned by the program- mer to an eight byte region within the on-board register file. 3.1 operand types the mcs-96 architecture supports a variety of data types likely to be useful in a control application. to avoid confusion, the name of an operand type is capital- ized. a ``byte'' is an unsigned eight bit variable; a ``byte'' is an eight bit unit of data of any type. bytes bytes are unsigned 8-bit variables which can take on the values between 0 and 255. arithmetic and relational operators can be applied to byte operands but the result must be interpreted in modulo 256 arithmetic. logical operations on bytes are applied bitwise. bits within bytes are labeled from 0 to 7, with 0 being the least significant bit. words words are unsigned 16-bit variables which can take on the values between 0 and 65535. arithmetic and relational operators can be applied to word operands but the result must be interpreted modulo 65536. logi- cal operations on words are applied bitwise. bits within words are labeled from 0 to 15 with 0 being the least significant bit. words must be aligned at even byte boundaries in the mcs-96 address space. the least significant byte of the word is in the even byte ad- dress and the most significant byte is in the next higher (odd) address. the address of a word is the address of its least significant byte. word operations to odd ad- dresses are not guaranteed to operate in a consistent manner. short-integers short-integers are 8-bit signed variables which can take on the values between b 128 and a 127. arithmetic operations which generate results outside of the range of a short-integer will set the overflow indicators in the program status word. the actual nu- meric result returned will be the same as the equivalent operation on byte variables. 9
80C196KB user's guide integers integers are 16-bit signed variables which can take on the values between b 32,768 and a 32,767. arith- metic operations which generate results outside of the range of an integer will set the overflow indicators in the program status word. the actual numeric result returned will be the same as the equivalent operation on word variables. integers conform to the same alignment and addressing rules as do words. bits bits are single-bit operands which can take on the boolean values of true and false. in addition to the nor- mal support for bits as components of byte and word operands, the 80C196KB provides for the di- rect testing of any bit in the internal register file. the mcs-96 architecture requires that bits be addressed as components of bytes or words, it does not support the direct addressing of bits that can occur in the mcs- 51 architecture. double-words double-words are unsigned 32-bit variables which can take on the values between 0 and 4,294,967,295. the mcs-96 architecture provides di- rect support for this operand type for shifts, as the divi- dend in a 32-by-16 divide and the product of a 16-by-16 multiply, and for double-word comparisons. for these operations a double-word variable must reside in the on-board register file of the 80C196KB and be aligned at an address which is evenly divisible by 4. a double-word operand is addressed by the address of its least significant byte. double-word opera- tions which are not directly supported can be easily implemented with two word operations. for consist- ency with intel provided software the user should adopt the conventions for addressing double-word op- erands which are discussed in section 3.5. long-integers long-integers are 32-bit signed variables which can take on the values between b 2,147,483,648 and a 2,147,483,647. the mcs-96 architecture provides di- rect support for this data type for shifts, as the dividend in a 32-by-16 divide and the product of a 16-by-16 mul- tiply, and for double-word comparisons. long-integers can also be normalized. for these operations a long-integer variable must reside in the onboard register file of the 80C196KB and be aligned at an address which is evenly divisible by 4. a long-integer is addressed by the address of its least significant byte. long-integer operations which are not directly supported can be easily implemented with two inte- ger operations. for consistency with intel provided software, the user should adopt the conventions for ad- dressing long operands which are discussed in sec- tion 3.6. 3.2 operand addressing operands are accessed within the address space of the 80C196KB with one of six basic addressing modes. some of the details of how these addressing modes work are hidden by the assembly language. if the pro- grammer is to take full advantage of the architecture, it is important that these details be understood. this sec- tion will describe the addressing modes as they are han- dled by the hardware. at the end of this section the addressing modes will be described as they are seen through the assembly language. the six basic address modes which will be described are termed register-di- rect, indirect, indirect with auto-increment, immediate, short-indexed, and long-indexed. several other useful addressing operations can be achieved by combining these basic addressing modes with specific registers such as the zero register or the stack pointer. register-direct references the register-direct mode is used to directly access a register from the 256 byte on-board register file. the register is selected by an 8-bit field within the instruc- tion and the register address must conform to the oper- and type's alignment rules. depending on the instruc- tion, up to three registers can take part in the calcula- tion. examples add ax,bx,cx ; ax: 4 bx 0 cx mul ax,bx ; ax: 4 ax*bx incb cl ; cl: 4 cl 0 1 10
80C196KB user's guide indirect references the indirect mode is used to access an operand by plac- ing its address in a word variable in the register file. the calculated address must conform to the alignment rules for the operand type. note that the indirect ad- dress can refer to an operand anywhere within the ad- dress space of the 80C196KB, including the register file. the register which contains the indirect address is selected by an eight bit field within the instruction. an instruction can contain only one indirect reference and the remaining operands of the instruction (if any) must be register-direct references. examples ld ax, [ ax ] ; ax: 4 mem word(ax) addb al,bl, [ cx ] ; al: 4 bl 0 mem byte(cx) pop [ ax ] ; mem word(ax): 4 mem word(sp); sp: 4 sp 0 2 indirect with auto-increment references this addressing mode is the same as the indirect mode except that the word variable which contains the in- direct address is incremented after it is used to address the operand. if the instruction operates on bytes or short-integers the indirect address variable will be incremented by one. if the instruction operates on words or integers the indirect address variable will be incremented by two. examples ld ax, [ bx ]0 ; ax: 4 mem word(bx); bx: 4 bx 0 2 addb al,bl, [ cx ]0 ; al: 4 bl 0 mem byte(cx); cx: 4 cx 0 1 push [ ax ]0 ; sp: 4 sp 1 2; ; mem word(sp): 4 mem word(ax) ; ax: 4 ax 0 2 immediate references this addressing mode allows an operand to be taken directly from a field in the instruction. for operations on byte or short-integer operands this field is eight bits wide. for operations on word or integer operands the field is 16 bits wide. an in- struction can contain only one immediate reference and the remaining operand(s) must be register-direct refer- ences. examples add ax, # 340 ; ax: 4 ax 0 340 push # 1234h ; sp: 4 sp 1 2; mem word(sp): 4 1234h divb ax, # 10 ; al: 4 ax/10; ah: 4 ax mod 10 short-indexed references in this addressing mode an eight bit field in the instruc- tion selects a word variable in the register file which contains an address. a second eight bit field in the in- struction stream is sign-extended and summed with the word variable to form the address of the operand which will take part in the calculation. since the eight bit field is sign-extended, the effective address can be up to 128 bytes before the address in the word variable and up to 127 bytes after it. an in- struction can contain only one short-indexed reference and the remaining operand(s) must be register-direct references. examples ld ax,12 [ bx ] ; ax: 4 mem word(bx 0 12) mulb ax,bl,3 [ cx ] ; ax: 4 bl*mem byte(cx 0 3) 11
80C196KB user's guide long-indexed references this addressing mode is like the short-indexed mode except that a 16-bit field is taken from the instruction and added to the word variable to form the address of the operand. no sign extension is necessary. an in- struction can contain only one long-indexed reference and the remaining operand(s) must be register-direct references. examples and ax,bx,table [ cx ] ; ax: 4 bx and mem word(table 0 cx) st ax,table [ bx ] ; mem word(table 0 bx): 4 ax addb al,bl,lookup [ cx ] ; al: 4 bl 0 mem byte(lookup 0 cx) zero register addressing the first two bytes in the register file are fixed at zero by the 80C196KB hardware. in addition to providing a fixed source of the constant zero for calculations and comparisons, this register can be used as the word variable in a long-indexed reference. this combination of register selection and address mode allows any loca- tion in memory to be addressed directly. examples add ax,1234 [ 0 ] ; ax: 4 ax 0 mem word(1234) pop 5678 [ 0 ] ; mem word(5678): 4 mem word(sp) ; sp: 4 sp 0 2 stack pointer register addressing the system stack pointer in the 80C196KB is accessed as register 18h of the internal register file. in addition to providing for convenient manipulation of the stack pointer, this also facilitates the accessing of operands in the stack. the top of the stack, for example, can be accessed by using the stack pointer as the word vari- able in an indirect reference. in a similar fashion, the stack pointer can be used in the short-indexed mode to access data within the stack. examples push [ sp ] ; duplicate top of stack ld ax,2 [ sp ] ; ax: 4 next to top assembly language addressing modes the mcs-96 assembly language simplifies the choice of addressing modes to be used in several respects: direct addressing. the assembly language will choose between register-direct addressing and long-indexed with the zero register depending on where the oper- and is in memory. the user can simply refer to an oper- and by its symbolic name: if the operand is in the regis- ter file, a register-direct reference will be used, if the operand is elsewhere in memory, a long-indexed refer- ence will be generated. indexed addressing. the assembly language will choose between short and long indexing depending on the value of the index expression. if the value can be expressed in eight bits then short indexing will be used, if it cannot be expressed in eight bits then long indexing will be used. these features of the assembly language simplify the programming task and should be used wherever possi- ble. 3.3 program status word the program status word (psw) is a collection of boo- lean flags which retain information concerning the state of the user's program. there are two bytes in the psw; the actual status word and the low byte of the interrupt mask. figure 3-1 shows the status bits of the psw. the psw can be saved in the system stack with a single operation (pushf) and restored in a like manner (popf). only the interrupt section of the psw can be accessed directly. there is no sfr for the psw status bits. 12
80C196KB user's guide condition flags the psw bits on the 80C196KB are set as follows: psw: 76543210 znvvtcx ist figure 3-1. psw register z: the z (zero) flag is set to indicate that the opera- tion generated a result equal to zero. for the add- with-carry (addc) and subtract-with-borrow (subc) operations the z flag is cleared if the re- sult is non-zero but is never set. these two in- structions are normally used in conjunction with the add and sub instructions to perform multi- ple precision arithmetic. the operation of the z flag for these instructions leaves it indicating the proper result for the entire multiple precision cal- culation. n: the negative flag is set to indicate that the opera- tion generated a negative result. note that the n flag will be in the algebraically correct state even if an overflow occurs. for shift operations, includ- ing the normalize operation and all three forms (shl, shr, shra) of byte, word and double word shifts, the n flag will be set to the same value as the most significant bit of the result. this will be true even if the shift count is 0. v: the overflow flag is set to indicate that the opera- tion generated a result which is outside the range for the destination data type. for the shl, shlb and shll instructions, the v flag will be set if the most significant bit of the operand changes at any time during the shift. for divide operations, the following conditions are used to determine if the v flag is set: for the operation: v is set if quotient is: unsigned byte divide l 255(0ffh) unsigned word divide l 65535(0ffffh) signed k b 127(81h) byte or divide l 127(7fh) signed k b 32767(8001h) word or divide l 32767(7fffh) vt: the overflow trap flag is set when the v flag is set, but it is only cleared by the clrvt, jvt and jnvt instructions. the operation of the vt flag allows for the testing for a possible overflow con- dition at the end of a sequence of related arithme- tic operations. this is normally more efficient than testing the v flag after each instruction. c: the carry flag is set to indicate the state of the arithmetic carry from the most significant bit of the alu for an arithmetic operation, or the state of the last bit shifted out of an operand for a shift. arithmetic borrow after a subtract operation is the complement of the c flag (i.e. if the operation generated a borrow then c e 0.) x: reserved. should always be cleared when writing to the psw for compatibility with future prod- ucts. i: the global interrupt disable bit disables all inter- rupts when cleared except nmi, trap, and un- implemented opcode. st: the st (sticky bit) flag is set to indicate that during a right shift a 1 has been shifted first into the c flag and then been shifted out. the st flag is undefined after a multiply operation. the st flag can be used along with the c flag to control rounding after a right shift. consider multiplying two eight bit quantities and then scaling the result down to 12 bits: mulub ax,cl,dl ;ax: 4 cl*dl shr ax, # 4 ;shift right 4 places if the c flag is set after the shift, it indicates that the bits shifted off the end of the operand were greater-than or equal-to one half the least significant bit (lsb) of the result. if the c flag is clear after the shift, it indicates that the bits shifted off the end of the operand were less than half the lsb of the result. without the st flag, the rounding decision must be made on the basis of the c flag alone. (normally the result would be rounded up if the c flag is set.) the st flag allows a finer resolution in the rounding decision: c st value of the bits shifted off 0 0 value e 0 010 k value k (/2 lsb 1 0 value e (/2 lsb 1 1 value l (/2 lsb figure 3-2. rounding alternatives imprecise rounding can be a major source of error in a numerical calculation; use of the st flag improves the options available to the programmer. 13
80C196KB user's guide interrupt flags the lower eight bits of the psw individually mask the lowest 8 sources of interrupt to the 80C196KB. these mask bits can be accessed as an eight bit byte (int e maskeaddress 8) in the on-board register file. a sep- arate register (int e mask1eaddress 13h) contains the control bits for the higher 8 interrupts. a logical `1' in these bit positions enables the servicing of the corre- sponding interrupt. bit 9 in the psw is the global inter- rupt disable. if this bit is cleared then interrupts will be locked out. note that the interrupts are collected in the int e pend registers even if they are locked out. exe- cution of the corresponding service routines will pro- ceed according to their priority when they become en- abled. further information on the interrupt structure of the 80C196KB can be found in section 5. 3.4 instruction set the mcs-96 instruction set contains a full set of arith- metic and logical operations for the 8-bit data types byte and short integer and for the 16-bit data types word and integer. the double-word and long data types (32 bits) are supported for the products of 16-by-16 multiplies and the dividends of 32-by-16 divides, for shift operations, and for 32-bit compares. the remaining operations on 32-bit variables can be implemented by combinations of 16-bit opera- tions. as an example the sequence: add ax,cx addc bx,dx performs a 32-bit addition, and the sequence sub ax,cx subc bx,dx performs a 32-bit subtraction. operations on real (i.e. floating point) variables are not supported directly by the hardware but are supported by the floating point library for the 80C196KB (fpal-96) which imple- ments a single precision subset of draft 10 of the ieee standard for floating point arithmetic. the performance of this software is significantly improved by the 80C196KB norml instruction which normalizes a 32-bit variable and by the existence of the st flag in the psw. in addition to the operations on the various data types, the 80C196KB supports conversions between these types. ldbze (load byte zero extended) converts a byte to a word and ldbse (load byte sign extend- ed) converts a short-integer into an integer. words can be converted to double-words by simply clearing the upper word of the double- word (clr) and integers can be converted to longs with the ext (sign extend) instruction. the mcs-96 instructions for addition, subtraction, and comparison do not distinguish between unsigned words and signed integers. conditional jumps are provided to allow the user to treat the results of these operations as either signed or unsigned quantities. as an example, the cmpb (compare byte) instruction is used to compare both signed and unsigned eight bit quantities. a jh (jump if higher) could be used following the compare if unsigned operands were involved or a jgt (jump if greater-than) if signed operands were involved. tables 3-1 and 3-2 summarize the operation of each of the instructions. complete descriptions of each instruc- tion and its timings can be found in the mcs-96 family instruction set chapter. the execution times for the instruction set are given in figure 3-3. these times are given for a 16-bit bus with no wait states. on-chip eprom/rom space is a 16- bit, zero wait state bus. when executing from an 8-bit external memory system or adding wait states, the cpu becomes bus limited and must sometimes wait for the prefetch queue. the performance penalty for an 8-bit external bus is difficult to measure, but has shown to be between 10 and 30 percent based on the instruction mix. the best way to measure code performance is to actually benchmark the code and time it using an emu- lator or with timer1. the indirect and indexed instruction timings are given for two memory spaces: sfr/internal ram space (0 0ffh), and a memory controller reference (100h 0ffffh). any instruction that uses an operand that is referenced through the memory controller (ex. add r1,5000h [ 0 ] ) takes 2 3 states longer than if the oper- and was in the sfr/internal ram space. any data access to on-chip rom/eprom is considered to be a memory controller reference. flag settings. the modification to the flag setting is shown for each instruction. a checkmark ( & ) means that the flag is set or cleared as appropriate. a hyphen means that the flag is not modified. a one or zero (1) or (0) indicates that the flag will be in that state after the instruction. an up arrow ( u ) indicates that the in- struction may set the flag if it is appropriate but will not clear the flag. a down arrow ( v ) indicates that the flag can be cleared but not set by the instruction. a question mark (?) indicates that the flag will be left in an indeterminant state after the operation. 14
80C196KB user's guide table 3-1a. instruction summary mnemonic operands operation (note 1) flags notes z n c v vt st add/addb 2 d w d a a &&&& u b add/addb 3 d w b a a &&&& u b addc/addcb 2 d w d a a a c v &&& u b sub/subb 2 d w d b a &&&& u b sub/subb 3 d w b b a &&&& u b subc/subcb 2 d w d b a a c b 1 v &&& u b cmp/cmpb 2 d b a &&&& u b mul/mulu 2 d,d a 2 w d c a bbbbb b 2 mul/mulu 3 d,d a 2 w b c a bbbbb b 2 mulb/mulub 2 d,d a 1 w d c a bbbbb b 3 mulb/mulub 3 d,d a 1 w b c a bbbbb b 3 divu 2 d w (d,d a 2) /a,d a 2 w remainder bbb & u b 2 divub 2 d w (d,d a 1) /a,d a 1 w remainder bbb & u b 3 div 2 d w (d,d a 2) /a,d a 2 w remainder bbb & u b divb 2 d w (d,d a 1) /a,d a 1 w remainder bbb & u b and/andb 2 d w d and a && 00 bb and/andb 3 d w b and a && 00 bb or/orb 2 d w dora && 00 bb xor/xorb 2 d w d (ecxl. or) a && 00 bb ld/ldb 2 d w a bbbbb b st/stb 2 a w d bbbbb b ldbse 2 d w a; d a 1 w sign(a) bbbbb b 3,4 ldbze 2 d w a; d a 1 w 0 bbbbb b 3,4 push 1 sp w sp b 2; (sp) w a bbbbb b pop 1 a w (sp); sp a 2 bbbbb b pushf 0 sp w sp b 2; (sp) w psw; 0 0 0 0 0 0 psw w 0000h; i w 0 popf 0 psw w (sp); sp w sp a 2; i w & &&&& & & sjmp 1 pc w pc a 11-bit offset bbbbb b 5 ljmp 1 pc w pc a 16-bit offset bbbbb b 5 br [ indirect ] 1pc w (a) bbbbb b scall 1 sp w sp b 2; bbbbb b 5 (sp) w pc; pc w pc a 11-bit offset lcall 1 sp w sp b 2; (sp) w pc; bbbbb b 5 pc w pc a 16-bit offset 15
80C196KB user's guide table 3-1b. instruction summary mnemonic operands operation (note 1) flags notes z n c v vt st ret 0 pc w (sp); sp w sp a 2 bbbb b b j (conditional) 1 pc w pc a 8-bit offset (if taken) b bbbb b b 5 jc 1 jump if c e 1 bbbb b b 5 jnc 1 jump if c e 0 bbbb b b 5 je 1 jump if z e 1 bbbb b b 5 jne 1 jump if z e 0 bbbb b b 5 jge 1 jump if n e 0 bbbb b b 5 jlt 1 jump if n e 1 bbbb b b 5 jgt 1 jump if n e 0 and z e 0 bbbb b b 5 jle 1 jump if n e 1orz e 1 bbbb b b 5 jh 1 jump if c e 1 and z e 0 bbbb b b 5 jnh 1 jump if c e 0orz e 1 bbbb b b 5 jv 1 jump if v e 1 bbbb b b 5 jnv 1 jump if v e 0 bbbb b b 5 jvt 1 jump if vt e 1; clear vt bbbb 0 b 5 jnvt 1 jump if vt e 0; clear vt bbbb 0 b 5 jst 1 jump if st e 1 bbbb b b 5 jnst 1 jump if st e 0 bbbb b b 5 jbs 3 jump if specified bit e 1 bbbb b b 5,6 jbc 3 jump if specified bit e 0 bbbb b b 5,6 djnz/ 1 d w d b 1; bbbb b b 5 djnzw if d i 0 then pc w pc a 8-bit offset 10 dec/decb 1 d w d b 1 &&&& u b neg/negb 1 d w 0 b d &&&& u b inc/incb 1 d w d a 1 &&&& u b ext 1 d w d; d a 2 w sign (d) && 00 bb 2 extb 1 d w d; d a 1 w sign (d) && 00 bb 3 not/notb 1 d w logical not (d) && 00 bb clr/clrb 1 d w 0 1000 bb shl/shlb/shll 2 c w msb-----lsb w 0 &&&& u b 7 shr/shrb/shrl 2 0 x msb-----lsb x c &&& 0 b & 7 shra/shrab/shral 2 msb x msb-----lsb x c &&& 0 b & 7 setc 0 c w 1 bb 1 bb b clrc 0 c w 0 bb 0 bb b 16
80C196KB user's guide table 3-1c. instruction summary mnemonic operands operation (note 1) flags notes z n c v vt st clrvt 0 vt w 0 bbbb 0 b rst 0 pc w 2080h 0 0 0 0 0 0 8 di 0 disable all interupts (i w 0) bbbb b b ei 0 enable all interupts (i w 1) bbbb b b nop 0 pc w pc a 1 bbbb b b skip 0 pc w pc a 2 bbbb b b norml 2 left shift till msb e 1; d w shift count && 0 bb b 7 trap 0 sp w sp b 2; bbbb b b 9 (sp) w pc; pc w (2010h) pusha 1 sp w sp-2; (sp) w psw; 0 0 0 0 0 0 psw w 0000h; sp w sp-2; (sp) w imask1/wsr; imask1 w 00h popa 1 imask1/wsr w (sp); sp w sp a 2 &&&& & & psw w (sp); sp w sp a 2 idlpd 1 idle mode if key e 1; bbbb b b powerdown mode if key e 2; chip reset otherwise cmpl 2 d-a &&&& u b bmov 2 [ ptr e hi ] a w [ ptr e low ] a ; bbbb b b until count e 0 notes: 1. if the mnemonic ends in ``b'' a byte operation is performed, otherwise a word operation is done. operands d, b, and a must conform to the alignment rules for the required operand type. d and b are locations in the register file; a can be located anywhere in memory. 2. d,d a 2 are consecutive words in memory; d is double-word aligned. 3. d,d a 1 are consecutive bytes in memory; d is word aligned. 4. changes a byte to word. 5. offset is a 2's complement number. 6. specified bit is one of the 2048 bits in the register file. 7. the ``l'' (long) suffix indicates double-word operation. 8. initiates a reset by pulling reset low. software should re-initialize all the necessary registers with code starting at 2080h. 9. the assembler will not accept this mnemonic. 10. the djnzw instruction is not guaranteed to work. see functional deviations section. 17
80C196KB user's guide table 3-2a. instruction length (in bytes)/opcode mnemonic direct immed indirect indexed normal * (1) a-inc * (1) short * (1) long * (1) add (3-op) 4/44 5/45 4/46 4/46 5/47 6/47 sub (3-op) 4/48 5/49 4/4a 4/4a 5/4b 6/4b add (2-op) 3/64 4/65 3/66 3/66 4/67 5/67 sub (2-op) 3/68 4/69 3/6a 3/6a 4/6b 5/6b addc 3/a4 4/a5 3/a6 3/a6 4/a7 5/a7 subc 3/a8 4/a9 3/aa 3/aa 4/ab 5/ab cmp 3/88 4/89 3/ab 3/ab 4/8b 5/8b addb (3-op) 4/54 4/55 4/56 4/56 5/57 6/57 subb (3-op) 4/58 4/59 4/5a 4/5a 5/5b 6/5b addb (2-op) 3/74 3/75 3/76 3/76 4/77 5/77 subb (2-op) 3/78 3/79 3/7a 3/7a 4/7b 5/7b addcb 3/b4 3/b5 3/b6 3/b6 4/b7 5/b7 subcb 3/b8 3/b9 3/ba 3/ba 4/bb 5/bb cmpb 3/98 3/99 3/9a 3/9a 4/9b 5/9b mul (3-op) 5/ (2) 6/ (2) 5/ (2) 5/ (2) 6/ (2) 7/ (2) mulu (3-op) 4/4c 5/4d 4/4e 4/4e 5/4f 6/4f mul (2-op) 4/ (2) 5/ (2) 4/ (2) 4/ (2) 5/ (2) 6/ (2) mulu (2-op) 3/6c 4/6d 3/6e 3/6e 4/6f 5/6f div 4/ (2) 5/ (2) 4/ (2) 4/ (2) 5/ (2) 6/ (2) divu 3/8c 4/8d 3/8e 3/8e 4/8f 5/8f mulb (3-op) 5/ (2) 5/ (2) 5/ (2) 5/ (2) 6/ (2) 7/ (2) mulub (3-op) 4/5c 4/5d 4/5e 4/5e 5/5f 6/5f mulb (2-op) 4/ (2) 4/ (2) 4/ (2) 4/ (2) 5/ (2) 6/ (2) mulub (2-op) 3/7c 3/7d 3/7e 3/7e 4/7f 5/7f divb 4/ (2) 4/ (2) 4/ (2) 4/ (2) 5/ (2) 6/ (2) divub 3/9c 3/9d 3/9e 3/9e 4/9f 5/9f and (3-op) 4/40 5/41 4/42 4/42 5/43 6/43 and (2-op) 3/60 4/61 3/62 3/62 4/63 5/63 or (2-op) 3/80 4/81 3/82 3/82 4/83 5/83 xor 3/84 4/85 3/86 3/86 4/87 5/87 andb (3-op) 4/50 4/51 4/52 4/52 5/53 5/53 andb (2-op) 3/70 3/71 3/72 3/72 4/73 4/73 orb (2-op) 3/90 3/91 3/92 3/92 4/93 5/93 xorb 3/94 3/95 3/96 3/96 4/97 5/97 push 2/c8 3/c9 2/ca 2/ca 3/cb 4/cb pop 2/cc e 2/ce 2/ce 3/cf 4/cf notes: 1. indirect and indirect a share the same opcodes, as do short and long indexed opcodes. if the second byte is even, use indirect or short indexed. if odd, use indirect or long indexed. 2. the opcodes for signed multiply and divide are the unsigned opcode with an ``fe'' prefix. 18
80C196KB user's guide table 3-2b. instruction length (in bytes)/opcode mnemonic direct immed indirect indexed normal a-inc short long ld 3/a0 4/a1 3/a2 3/a2 4/a3 5/a3 ldb 3/b0 3/b1 3/b2 3/b2 4/b3 5/b3 st 3/c0 e 3/c2 3/c2 4/c3 5/c3 stb 3/c4 e 3/c6 3/c6 4/c7 5/c7 ldbse 3/bc 3/bd 3/be 3/be 4/bf 5/bf lbsze 3/ac 3/ad 3/ae 3/ae 4/af 5/af mnemonic length/opcode pushf 1/f2 popf 1/f3 pusha 1/f4 popa 1/f5 trap 1/f7 lcall 3/ef scall 2/28 2f (3) ret 1/f0 ljmp 3/e7 sjmp 2/20 27 (3) br [] 2/e3 jnst 1/d0 jst 1/d8 jnh 1/d1 jh 1/d9 jgt 1/d2 jle 1/da jnc 1/b3 jc 1/d8 jnvt 1/d4 jvt 1/dc jnv 1/d5 jv 1/dd jge 1/d6 jlt 1/de jne 1/d7 je 1/df jbc 3/30 37 jbs 3/38 3f mnemonic length/opcode djnz 3/e0 djnzw 3/e1 (4) norml 3/0f shrl 3/0c shll 3/0d shral 3/0e shr 3/08 shrb 3/18 shl 3/09 shlb 3/19 shra 3/0a shrab 3/1a clrc 1/f8 setc 1/f9 di 1/fa ei 1/fb clrvt 1/fc nop 1/fd rst 1/ff skip 2/00 idlpd 1/f6 bmov 3/c1 notes: 3. the 3 least significant bits of the opcode are concatenated with the 8 bits to form an 11-bit, 2's complement offset. 4. the djnzw instruction is not guaranteed to work. see functional deviations section. 19
80C196KB user's guide table 3.3a. instruction execution state times (1) mnemonic direct immed indirect indexed normal * a-inc * short * long * add (3-op) 5 6 7/10 8/11 7/10 8/11 sub (3-op) 5 6 7/10 8/11 7/10 8/11 add (2-op) 4 5 6/8 7/9 6/8 7/9 sub (2-op) 4 5 6/8 7/9 6/8 7/9 addc 4 5 6/8 7/9 6/8 7/9 subc 4 5 6/8 7/9 6/8 7/9 cmp 4 5 6/8 7/9 6/8 7/9 addb (3-op) 5 5 7/10 8/11 7/10 8/11 subb (3-op) 5 5 7/10 8/11 7/10 8/11 addb (2-op) 4 4 6/8 7/9 6/8 7/9 subb (2-op) 4 4 6/8 7/9 6/8 7/9 addcb 4 4 6/8 7/9 6/8 7/9 subcb 4 4 6/8 7/9 6/8 7/9 cmpb 4 4 6/8 7/9 6/8 7/9 mul (3-op) 16 17 18/21 19/22 19/22 20/23 mulu (3-op) 14 15 16/19 17/19 17/20 18/21 mul (2-op) 16 17 18/21 19/22 19/22 20/23 mulu (2-op) 14 15 16/19 17/19 17/20 18/21 div 26 27 28/31 29/32 29/32 30/33 divu 24 25 26/29 27/30 27/30 28/31 mulb (3-op) 12 12 14/17 13/15 15/18 16/19 mulub (3-op) 10 10 12/15 12/16 12/16 14/17 mulb (2-op) 12 12 14/17 15/18 15/18 16/19 mulub (2-op) 10 10 12/15 13/15 12/16 14/17 divb 18 18 20/23 21/24 21/24 22/25 divub 16 16 18/21 19/22 19/22 20/23 and (3-op) 5 6 7/10 8/11 7/10 8/11 and (2-op) 4 5 6/8 7/9 6/8 7/9 or (2-op) 4 5 6/8 7/9 6/8 7/9 xor 4 5 6/8 7/9 6/8 7/9 andb (3-op) 5 5 7/10 8/11 7/10 8/11 andb (2-op) 4 4 6/8 7/9 6/8 7/9 orb (2-op) 4 4 6/8 7/9 6/8 7/9 xorb 4 4 6/8 7/9 6/8 7/9 ld, ldb 4, 4 5, 4 5/8 6/8 6/9 7/10 st, stb 4, 4 b 5/8 6/9 6/9 7/10 ldbse 4 4 5/8 6/8 6/9 7/10 ldbze 4 4 5/8 6/8 6/9 7/10 bmov internal/internal: 6 a 8 per word external/internal: 6 a 11 per word external/external: 6 a 14 per word push (int stack) 6 7 9/12 10/13 10/13 11/14 pop (int stack) 8 b 10/12 11/13 11/13 12/14 push (ext stack) 8 9 11/14 12/15 12/15 13/16 pop (ext stack) 11 b 13/15 14/16 14/16 15/17 * times for operands as: sfrs and internal ram (0 1ffh)/memory controller (200h 0ffffh) note: 1. execution times for memory controller references may be one to two states higher depending on the number of bytes in the prefetch queue. internal stack is 200h 1ffh and external stack is 200h 0ffffh. 20
80C196KB user's guide table 3.3b. instruction execution state times mnemonic mnemonic pushf (int stack) 6 pushf (ext stack) 8 popf (int stack) 7 popf (ext stack) 10 pusha (int stack) 12 pusha (ext stack) 18 popa (int stack) 12 popa (ext stack) 18 trap (int stack) 16 trap (ext stack) 18 lcall (int stack) 11 lcall (ext stack) 13 scall (int stack) 11 scall (ext stack) 13 ret (int stack) 11 ret (ext stack) 14 cmpl 7 dec/decb 3 clr/clrb 3 ext/extb 4 not/notb 3 inc/incb 3 neg/negb 3 ljmp 7 sjmp 7 br [ indirect ] 7 jnst, jst 4/8 jump not taken/jump taken jnh, jh 4/8 jump not taken/jump taken jgt, jle 4/8 jump not taken/jump taken jnc, jc 4/8 jump not taken/jump taken jnvt, jvt 4/8 jump not taken/jump taken jnv, jv 4/8 jump not taken/jump taken jge, jlt 4/8 jump not taken/jump taken jne, je 4/8 jump not taken/jump taken jbc, jbs 5/9 jump not taken/jump taken djnz 5/9 jump not taken/jump taken djnzw (note 1) 5/9 jump not taken/jump taken norml 8 a 1 per shift (9 for 0 shift) shrl 7 a 1 per shift (8 for 0 shift) shll 7 a 1 per shift (8 for 0 shift) shral 7 a 1 per shift (8 for 0 shift) shr/shrb 6 a 1 per shift (7 for 0 shift) shl/shlb 6 a 1 per shift (7 for 0 shift) shra/shrab 6 a 1 per shift (7 for 0 shift) clrc 2 setc 2 di 2 ei 2 clrvt 2 nop 2 rst 15 (includes fetch of configuration byte) skip 3 idlpd 8/25 (proper key/improper key) note: 1. the djnzw instruction is not guaranteed to work. see functional deviations section. 21
80C196KB user's guide 3.5 80C196KB instruction set additions and differences for users already familiar with the 8096bh, there are six instructions added to the standard mcs-96 instruc- tion set to form the 80C196KB instruction set. all of the former instructions perform the same function, ex- cept as indicated in the next section. the new instruc- tions and their descriptions are listed below: pusha e pushes the psw, int e mask, im- ask1, and wsr popa e pops the psw, int e mask, imask1, and wsr idlpd e sets the part into idle or powerdown mode cmpl e compare 2 long direct values bmov e block move using 2 auto-incrementing pointers and a counter djnzw e decrement jump not zero using a word counter (not functional on current step- ping.) instruction differences instruction times on the 80C196KB are shorter than those on the 8096 for many instructions. for example a 16 c 16 unsigned multiply has been reduced from 25 to 14 states. in addition, many zero and one operand in- structions and most instructions using external data take one or two fewer state times. indexed and indirect operations relative to the stack pointer (sp) work differently on the 80C196KB than on the 8096bh. on the 8096bh, the address is calcu- lated based on the un-updated version of the stack pointer. the 80C196KB uses the updated version. the offset for pop [ sp ] and pop nn [ sp ] instructions may need to be changed by a count of 2. 3.6 software standards and conventions for a software project of any size it is a good idea to modularize the program and to establish standards which control the communication between these mod- ules. the nature of these standards will vary with the needs of the final application. a common component of all of these standards, however, must be the mechanism for passing parameters to procedures and returning re- sults from procedures. in the absence of some overrid- ing consideration which prevents their use, it is suggest- ed that the user conform to the conventions adopted by the plm-96 programming language for procedure link- age. it is a very usable standard for both the assembly language and plm-96 environment and it offers com- patibility between these environments. another advan- tage is that it allows the user access to the same floating point arithmetics library that plm-96 uses to operate on real variables. register utilization the mcs-96 architecture provides a 256 byte register file. some of these registers are used to control register- mapped i/o devices and for other special functions such as the zero register and the stack pointer. the remaining bytes in the register file, some 230 of them, are available for allocation by the programmer. if these registers are to be used effectively, some overall strategy for their allocation must be adopted. plm-96 adopts the simple and effective strategy of allocating the eight bytes between addresses 1ch and 23h as temporary storage. the starting address of this region is called plmreg. the remaining area in the register file is treated as a segment of memory which is allocated as required. addressing 32-bit operands these operands are formed from two adjacent 16-bit words in memory. the least significant word of the double word is always in lower address, even when the data is in the stack (which means that the most signifi- cant word must be pushed into the stack first). a dou- ble word is addressed by the address of its least signifi- cant byte. note that the hardware supports some opera- tions on double words. for these operations the double word must be in the internal register file and must have an address which is evenly divisible by four. subroutine linkage parameters are passed to subroutines in the stack. pa- rameters are pushed into the stack in the order that they are encountered in the scanning of the source text. eight-bit parameters (bytes or short-inte- gers) are pushed into the stack with the high order byte undefined. thirty-two bit parameters (long-in- tegers, double-words, and reals) are pushed onto the stack as two 16-bit values; the most significant half of the parameter is pushed into the stack first. as an example, consider the following plm-96 proce- dure: example e procedure: procedure (param1,param2,param3); declare param1 byte, param2 dword, param3 word; 22
80C196KB user's guide when this procedure is entered at run time the stack will contain the parameters in the following order: ?????? : param1 high word of param2 low word of param2 param3 return address w stack e pointer figure 3-5. stack image if a procedure returns a value to the calling code (as opposed to modifying more global variables) then the result is returned in the variable plmreg. plmreg is viewed as either an 8-, 16- or 32-bit variable depend- ing on the type of the procedure. the standard calling convention adopted by plm-96 has several key features: a) procedures can always assume that the eight bytes of register file memory starting at plmreg can be used as temporaries within the body of the proce- dure. b) code which calls a procedure must assume that the eight bytes of register file memory starting at plmreg are modified by the procedure. c) the program status word (pswesee section 3.3) is not saved and restored by procedures so the calling code must assume that the condition flags (z, n, v, vt, c, and st) are modified by the procedure. d) function results from procedures are always re- turned in the variable plmreg. plm-96 allows the definition of interrupt proce- dures which are executed when a predefined interrupt occurs. these procedures do not conform to the rules of a normal procedure. parameters cannot be passed to these procedures and they cannot return results. since they can execute essentially at any time (hence the term interrupt), these procedures must save the psw and plmreg when they are entered and restore these val- ues before they exit. 3.7 software protection hints several features to assist in recovery from hardware and software errors are available on the 80C196KB. protection is also provided against executing unimple- mented opcodes by the unimplemented opcode inter- rupt. in addition, the hardware reset instruction (rst) can cause a reset if the program counter goes out of bounds. this instruction has an opcode of 0ffh, so if the processor reads in bus lines which have been pulled high it will reset itself. it is recommended that unused areas of code be filled with nops and periodic jumps to an error routine or rst (reset chip) instructions. this is particularly im- portant in the code around lookup tables, since if look- up tables are executed undesired results will occur. wherever space allows, each table should be surround- ed by 7 nops (the longest 80C196KB instruction has 7 bytes) and a rst or jump to error routine instruction. since rst is a one-byte instruction, the nops are not needed if rsts are used instead of jumps to an error routine. this will help to ensure a speedy recovery should the processor have a glitch in the program flow. the watchdog timer (wdt) further protects against software and hardware errors. when using the wdt to protect software it is desirable to reset it from only one place in code, lessening the chance of an undesired wdt reset. the section of code that resets the wdt should monitor the other code sections for proper oper- ation. this can be done by checking variables to make sure they are within reasonable values. simply using a software timer to reset the wdt every 10 milliseconds will provide protection only for catastrophic failures. 4.0 peripheral overview there are five major peripherals on the 80C196KB: the pulse-width-modulated output (pwm), timer1 and timer2, high speed i/o unit, serial port and a/d converter. with the exception of the high speed i/o unit (hsio), each of the peripherals is a single unit that can be discussed without further separation. four individual sections make up the hsio and work together to form a very flexible timer/counter based i/o system. included in the hsio are a 16-bit timer (timer1), a 16-bit up/down counter (timer2), a pro- grammable high speed input unit (hsi), and a pro- grammable high speed output unit (hso). with very little cpu overhead the hsio can measure pulse widths, generate waveforms, and create periodic inter- rupts. depending on the application, it can perform the work of up to 18 timer/counters and capture/compare registers. a brief description of the peripheral functions and in- terractions is included in this section. it provides over- view information prior to the detailed discussions in the following sections. all of the details on control bits and precautions are in the individual sections for each pe- ripheral starting with section 5. 23
80C196KB user's guide 4.1 pulse width modulation output (d/a) digital to analog conversion can be done with the pulse width modulation output. the output waveform is a variable duty cycle pulse which repeats every 256 state times or 512 state times if the prescaler is enabled. changes in the duty cycle are made by writing to the pwm register. there are several types of motors which require a pwm waveform for most efficient operation. additionally, if this waveform is integrated it will pro- duce a dc level which can be changed in 256 steps by varying the duty cycle. details on the pwm are in sec- tion 6. 4.2 timers two 16-bit timers are available for use on the 80C196KB. the first is designated ``timer1'', the sec- ond ``timer2''. timer1 is used to synchronize events to real time, while timer2 is clocked externally and syn- chronizes events to external occurrences. the timers are the time bases for the high speed input (hsi) and high speed output (hso) units and can be considered an integral part of the hsi/o. details on the timers are in section 7. timer1 is a free-running timer which is incremented every eight state times, just as it is on the 8096bh. timer1 can cause an interrupt when it overflows. timer2 counts transitions, both positive and negative, on its input which can be either the t2clk pin or the hsi.1 pin. timer2 can be read and written and can be reset by hardware, software or the hso unit. it can be used as an up/down counter based on port 2.6 and it's value can be captured into the t2capture register. in- terrupts can be generated on capture events and if tim- er2 crosses the 0ffffh/0000h boundary or the 7fffh/8000h boundary in either direction. 4.3 high speed inputs (hsi) the high speed input (hsi) unit can capture the value of timer1 when an event takes place on one of four input pins (hsi.0-hsi.3). four types of events can trig- ger a capture: rising edges only, falling edges only, ris- ing or falling edges, or every eighth rising edge. a block diagram of this unit is shown in figure 4-3. details on the hsi unit are in section 8. when events occur, the timer1 value gets stored in the fifo along with 4 status bits which indicate the input line(s) that caused the event. the next event ready to be unloaded from the fifo is placed in the hsi holding register, so a total of 8 pieces of data can be stored in the fifo. data is taken off the fifo by reading the hsi e status register, followed by reading the hsi e time register. when the time register is read the next fifo location is loaded into the holding regis- ter. three forms of hsi interrupts can be generated: when a value moves from the fifo into the holding register; when the fifo (independent of the holding register) has 4 or more events stored; and when the fifo has 6 or more events stored. this flexibility allows optimiza- tion of the hsi for the expected frequency of interrupts. independent of the hsi operation, the state of the hsi pins is indicated by 4 bits of the hsi e status regis- ter. also independent of the hsi operation is the hsi.0 pin interrupt, which can be used as an extra external interrupt even if the pin is not enabled to the hsi unit. 4.4 high speed outputs (hso) the high speed output (hso) unit can generate events at specified times or counts based on timer1 or timer2 with minimal cpu overhead. a block diagram of the hso unit is shown in figure 4-4. up to 8 pending events can be stored in the cam (content addressable memory) of the hso unit at one time. commands are placed into the hso unit by first writing to hso e command with the event to occur, and then to hso e time with the timer match value. fourteen different types of events can be triggered by the hso: 8 external and 6 internal. there are two inter- rupt vectors associated with the hso, one for external events, and one for internal events. external events con- sist of switching one or more of the 6 hso pins (hso.0-hso.5). internal events include setting up 4 software timers, resetting timer2, and starting an a/ d conversion. the software timers are flags that can be set by the hso and optionally cause interrupts. details on the hso unit are in section 9. 4.5 serial port the serial port on the 80C196KB is functionally com- patible with the serial port on the mcs-51 and mcs-96 families of microcontrollers. one synchronous and three asynchronous modes are available. the asynchro- nous modes are full duplex, meaning they can transmit and receive at the same time. double buffering is pro- vided for the receiver so that a second byte can be re- ceived before the first byte has been read. the transmit- ter is also double buffered, allowing bytes to be written while transmission is still in progress. the serial port status (sp e stat) register contains bits to indicate receive overrun, parity, and framing er- rors, and transmit and receive interrupts. details on the serial port are in section 10. 24
80C196KB user's guide hsi trigger options 270651 18 270651 19 figure 4-3. hsi block diagram high speed output controls 6 pins 4 software timers 2 interrupts initiate a/d conversion reset timer2 270651 8 figure 4-4. hso block diagram 25
80C196KB user's guide modes of operation mode 0 is a synchronous mode which is commonly used for shift register based i/o expansion. sets of 8 bits are shifted in or out of the 80C196KB with a data signal and a clock signal. mode 1 is the standard asynchronous communications mode: the data frame used in this mode consists of 10 bits: a start bit (0), 8 data bits (lsb first), and a stop bit (1). parity can be enabled to send an even parity bit instead of the 8th data bit and to check parity on recep- tion. modes 2 and 3 are 9-bit modes commonly used for multi-processor communications. the data frame used in these modes consist of a start bit (0), 9 data bits (lsb first), and a stop bit (1). when transmitting, the 9th data bit can be set to a one to indicate an address or other global transmission. devices in mode 2 will be interrupted only if this bit is set. devices in mode 3 will be interrupted upon any reception. this provides an easy way to have selective reception on a data link. mode 3 can also be used to send and receive 8 bits of data plus even parity. baud rates baud rates are generated in an independent 15-bit counter based on either the t2clk pin or xtal1 pin. common baud rates can be easily generated with stan- dard crystal frequencies. a maximum baud rate of 750 kbaud is available in the asynchronous modes with 12mhz on xtal1. the synchronous mode has a max- imum rate of 3.0 mbaud with a 12 mhz clock. 4.6 a/d converter the 80C196KB's analog interface consists of a sample- and-hold, an 8-channel multiplexer, and a 10-bit suc- cessive approximation analog-to-digital converter. analog signals can be sampled by any of the 8 analog input pins (ach0 through ach7) which are shared with port 0. an a/d conversion is performed on one input at a time using successive approximation with a result equal to the ratio of the input voltage divided by the analog supply voltage. if the ratio is 1.00, then the result will be all ones. a conversion can be started by writing to the a/d e command register or by an hso command. details on the a/d converter are in section 11. 4.7 i/o ports there are five 8-bit i/o ports on the 80C196KB. some of these ports are input only, some are output only, some are bidirectional and some have multiple func- tions. in addition to these ports, the hsi/o pins can be used as standard i/o pins if their timer related features are not needed. port 0 is an input port which is also the analog input for the a/d converter. port 1 is a quasi-bidirectional port and the 3msbs of port 1 are multiplexed with the hold /hlda functions. port 2 contains three types of port lines: quasi-bidirectional, input and output. its input and output lines are shared with other functions such as serial port receive and transmit and timer2 clock and reset. ports 3 and 4 are open-drain bidirec- tional ports which share their pins with the address/ data bus. quasi-bidirectional pins can be used as input and out- put pins without the need for a data direction register. they output a strong low value and a weak high value. the weak high value can be externally pulled low pro- viding an input function. a detailed explanation of these ports can be found in section 12. 4.8 watchdog timer the watchdog timer (wdt) provides a means to re- cover gracefully from a software upset. when the watchdog is enabled it will initiate a hardware reset unless the software clears it every 64k state times. hardware resets on the 80C196KB cause the reset input pin to be pulled low, providing a reset signal to other components on the board. the wdt is indepen- dent of the other timers on the 80C196KB. 26
80C196KB user's guide 5.0 interrupts twenty-eight (28) sources of interrupts are available on the 80C196KB. these sources are gathered into 15 vec- tors plus special vectors for nmi, the trap instruc- tion, and unimplemented opcodes. figure 5-1 shows the routing of the interrupt sources into their vectors as well as the control bits which enable some of the sources. special interrupts three special interrupts are available on the 80C196KB: nmi, trap and unimplemented opcode. the external nmi pin generates an unmaskable inter- rupt for implementation of critical interrupt routines. the trap instruction is useful in the development of custom software debuggers or generation of software interrupts. the unimplemented opcode interrupt gener- ates an interrupt when unimplemented opcodes are exe- 270651 9 figure 5-1. 80C196KB interrupt sources 27
80C196KB user's guide cuted. this provides software recovery from random execution during hardware and software failures. al- though available for customer use, these interrupts may be used in intel development tools or evaluation boards. nmi nmi, the external non-maskable interrupt, is the highest priority interrupt. it vectors indirectly through location 203eh. for design symmetry, a mask bit ex- ists in int e mask1 for the nmi. to prevent acci- dental masking of an nmi, the bit does not function and will not stop an nmi from occurring. for future compatibility, the nmi mask bit must be set to zero. nmi on the 8096 vectored directly to location 0000h, so for the 80C196KB to be compatible with 8096 soft- ware, which uses the nmi, location 203eh must be loaded with 0000h. the nmi interrupt vector and in- terrupt vector location is used by some intel develop- ment tools. for example, the ev80C196KB evaluation board uses the nmi to process serial communication interrupts from the host. the nmi interrupt routine executes monitor commands passed from the host. the nmi interrupt is sampled during ph1 or clkout low and is latched internally. if the pin is held high, multiple interrupts will not occur. trap opcode 0f7h, the trap instruction, causes an indi- rect vector through location 2010h. the trap in- struction provides a single instruction interrupt useful in designing software debuggers. the trap instruc- tion prevents the acknowledgement of interrupts until after execution of the next instruction. unimplemented opcode opcodes which are not implemented on the 80C196KB will cause an indirect vector through location 2012h. user code or hardware which may have failed and run into an unimplemented opcode can software recover through this interrupt. the djnzw instruction is not supported on the 80C196KB but remains a valid op- code, therefore, no interrupt will occur. the programmer must initialize the interrupt vector ta- ble with the starting addresses of the appropriate inter- rupt service routines. it is suggested that any unused interrupts be vectored to an error handling routine. in a debug environment, it may be desirable to have the rou- tine lock into a jump to self loop which would be easily traceable with emulation tools. more sophisticated rou- tines may be appropriate for production code recover- ies. 270651 10 figure 5-2. 80C196KB interrupt structure block diagram five registers control the operation of the interrupt sys- tem: int e pend, int e pend1, int e mask and int e mask1 and the psw which contains a global disable bit. a block diagram of the system is shown in figure 5-2. the transition detector looks for 0 to 1 tran- sitions on any of the sources. external sources have a maximum transition speed of one edge every state time. sampling will be guaranteed if the level on the interrupt line is held for at least one state time. if the interrupt line is not held for at least one state time, the interrupt may not be detected. 28
80C196KB user's guide 5.1 interrupt control interrupt pending register when the hardware detects one of the sixteen inter- rupts it sets the corresponding bit in one of two pending interrupt registers (int e pend-09h and int e pend1-12h). when the interrupt vector is taken, the pending bit is cleared. these registers, the formats of which are shown in figure 5-3, can be read or modified as byte registers. they can be read to determine which of the interrupts are pending at any given time or modi- fied to either clear pending interrupts or generate inter- rupts under software control. any software which modifies the int e pend registers should ensure that the entire operation is inseparable. the easiest way to do this is to use the logical instructions in the two or three operand format, for example: andb int pend, # 11111101b ; clears the a/d interrupt orb int pend, # 00000010b ; sets the a/d interrupt caution must be used when writing to the pending reg- ister to clear interrupts. if the interrupt has already been acknowledged when the bit is cleared, a 5 state time ``partial'' interrupt cycle will occur. this is be- cause the 80C196KB will have to fetch the next instruc- tion of the normal instruction flow, instead of proceed- ing with the interrupt processing. the effect on the pro- gram will be essentially that of an extra two nops. this can be prevented by clearing the bits using a 2 operand immediate logical, as the 80C196KB holds off acknowledging interrupts during these ``read/modify/ write'' instructions. interrupt mask register individual interrupts can be enabled or disabled by set- ting or clearing bits in the interrupt mask registers (int e mask-08h and int e mask1-13h). the format of these registers is the same as that of the inter- rupt pending register shown in figure 5-3. the int e mask and int e mask1 registers can be read or written as byte registers. a one in any bit posi- tion will enable the corresponding interrupt source and a zero will disable the source. the hardware will save any interrupts that occur by setting bits in the pending register, even if the interrupt mask bit is cleared. the int e mask register is the lower eight bits of the psw so the pushf and popf instructions save and restore the int e mask register as well as the global interrupt lockout and the arithmetic flags. both the int e mask and int e mask1 registers can be saved with the pusha and popa instructions. global disable the processing of all interrupts except the nmi, trap and unimplemented opcode interrupts can be disabled by clearing the i bit in the psw. setting the i bit will enable interrupts that have mask register bits which are set. the i bit is controlled by the ei (enable interrupts) and di (disable interrupts) instructions. note that the i bit only controls the actual servicing of interrupts. interrupts that occur during periods of lockout will be held in the pending register and serviced on a priori- tized basis when the lockout period ends. 5.2 interrupt priorities the priority encoder looks at all of the interrupts which are both pending and enabled, and selects the one with the highest priority. the priorities are shown in figure 5-4 (15 is highest, 0 is lowest). the interrupt generator then forces a call to the location in the indicated vector location. this location would be the starting location of the interrupt service routine (isr). 76543210 12h ipend1: nmi fifo ext t2 t2 hsi4 ri ti 13h imask1: full int1 ovf cap 76543210 09h ipend: ext ser soft hsi.0 hso hsi a/d timer 08h imask: int port timer pin pin data done ovf figure 5-3. interrupt mask and pending registers 29
80C196KB user's guide number source vector priority location int15 nmi 203eh 15 int14 hsi fifo full 203ch 14 int13 extint1 203ah 13 int12 timer2 overflow 2038h 12 int11 timer2 capture 2036h 11 int10 4th entry into hsi fifo 2034h 10 int09 ri 2032h 9 int08 ti 2030h 8 special unimplemented opcode 2012h n/a special trap 2010h n/a int07 extint 200eh 7 int06 serial port 200ch 6 int05 software timer 200ah 5 int04 hsi.0 pin 2008h 4 int03 high speed outputs 2006h 3 int02 hsi data available 2004h 2 int01 a/d conversion complete 2002h 1 int00 timer overflow 2000h 0 figure 5-4. 80C196KB interrupt priorities this priority selection controls the order in which pending interrupts are passed to the software via inter- rupt calls. the software can then implement its own priority structure by controlling the mask registers (int e mask and int e mask1). to see how this is done, consider the case of a serial i/o service routine which must run at a priority level which is lower than the hsi data available interrupt but higher than any other source. the ``preamble'' and exit code for this interrupt service routine would look like this: serial io isr: pusha ; save the psw, int mask ; int mask1, and wsr ldb int mask, # 00000100b ei ; enable interrupts again ; ; ; ; service the interrupt ; ; ; popa ; restore ret note that location 200ch in the interrupt vector table would have to be loaded with the label serial e io e isr and the interrupt be enabled for this routine to execute. there is an interesting chain of instruction side-effects which makes this (or any other) 80C196KB interrupt service routine execute properly: a) after the interrupt controller decides to process an interrupt, it executes a ``call'', using the location from the corresponding interrupt vector table entry as the destination. the return address is pushed onto the stack. another interrupt cannot be serviced until after the first instruction following the inter- rupt call is executed. b) the pusha instruction, which is now guaran- teed to execute, saves the psw, int e mask, int e mask1, and the wsr on the stack as two words, and clears them. an interrupt cannot be serviced immediately following a pusha instruc- tion. (if int e mask1 and the wsr register are not used, or 8096bh code is being executed, pushf, which saves only the psw and int e mask, can be used in place of pusha). c) ld int e mask, which is guaranteed to execute, enables those interrupts that are allowed to inter- rupt this isr. this allows the software to establish its own priorities independent of the hardware. d) the ei instruction reenables the processing of inter- rupts with the new priorities. e) at the end of the isr, the popa instruction re- stores the psw, int e mask, int e mask1, and wsr to their original state when the interrupt oc- curred. interrupts cannot occur immediately follow- ing a popa instruction so the ret instruction is guaranteed to execute. this prevents the stack from overflowing if interrupts are occurring at high fre- quency. (if int e mask1 and the wsr are not being used, or 8096bh code is being executed, popf, which restores only the psw and int e mask, can be used in place of popa.) 30
80C196KB user's guide notice that the ``preamble'' and exit code for the inter- rupt service routine does not include any code for sav- ing or restoring registers. this is because it has been assumed that the interrupt service routine has been al- located its own private set of registers from the on- board register file. the availability of some 230 bytes of register storage makes this quite practical. 5.3 critical regions interrupt service routines must sometimes share data with other routines. whenever the programmer is cod- ing those sections of code which access these shared pieces of data, great care must be taken to ensure that the integrity of the data is maintained. consider clear- ing a bit in the interrupt pending register as part of a non-interrupt routine: ldb al,int pend andb al, # bit mask stb al,int pend this code works if no other routines are operating con- currently, but will cause occasional but serious prob- lems if used in a concurrent environment. (all pro- grams which make use of interrupts must be considered to be part of a concurrent environment.) to demon- strate this problem, assume that the int e pend reg- ister contains 00001111b and bit 3 (hso event inter- rupt pending) is to be reset. the code does work for this data pattern but what happens if an hsi interrupt oc- curs somewhere between the ldb and the stb instruc- tions? before the ldb instruction int e pend con- tains 00001111b and after the ldb instruction so does al. if the hsi interrupt service routine executes at this point then int e pend will change to 00001011b. the andb changes al to 00000111b and the stb changes int e pend to 00000111b. it should be 00000011b. this code sequence has managed to gener- ate a false hsi interrupt the same basic process can generate an amazing assortment of problems and head- aches. these problems can be avoided by assuring mu- tual exclusion which basically means that if more than one routine can change a variable, then the program- mer must ensure exclusive access to the variable during the entire operation on the variable. in many cases the instruction set of the 80C196KB al- lows the variable to be modified with a single instruc- tion. the code in the above example can be implement- ed with a single instruction. andb int pend, # bit mask instructions are indivisible so mutual exclusion is en- sured in this case. changes to the int e pend or int e pend1 register must be made as a single in- struction, since bits can be changed in this register even if interrupts are disabled. depending on system config- urations, several other sfrs might also need to be changed in a single instruction for the same reason. when variables must be modified without interruption, and a single instruction can not be used, the program- mer must create what is termed a critical region in which it is safe to modify the variable. one way to do this is to simply disable interrupts with a di instruc- tion, perform the modification, and then re-enable in- terrupts with an ei instruction. the problem with this approach is that it leaves the interrupts enabled even if they were not enabled at the start. a better solution is to enter the critical region with a pushf instruction which saves the psw and also clears the interrupt en- able flags. the region can then be terminated with a popf instruction which returns the interrupt enable to the state it was in before the code sequence. it should be noted that some system configurations might require more protection to form a critical region. an example is a system in which more than one processor has ac- cess to a common resource such as memory or external i/o devices. 5.4 interrupt timing the 80C196KB can be interrupted from four different external sources; nmi, p2.2, hsi.0 and p0.7. all exter- nal interrupts are sampled during ph1 or clkout low and are latched internally. holding levels on exter- nal interrupts for at least one state time will ensure recognition of the interrupts. the external interrupts on the 80C196KB, although sampled during ph1, are edge triggered interrupts as opposed to level triggered. edge triggered interrupts will generate only one interrupt if the input is held high. on the other hand, level triggered interrupts will generate multiple interrupts when held high. interrupts are not always acknowledged immediately. if the interrupt signal does not occur prior to 4 state- times before the end of an instruction, the interrupt may not be acknowledged until after the next instruc- tion has been executed. this is because an instruction is fetched and prepared for execution a few state times before it is actually executed. there are 6 instructions which always inhibit interrupts from being acknowledged until after the next instruc- tion has been executed. these instructions are: ei, di e enable and disable all interrupts by tog- gling the global disable bit (psw.9). pushf e push flags pushes the psw/int e mask pair then clears it, leaving both int e mask and psw.9 clear. 31
80C196KB user's guide popf e pop flags pops the psw/int e mask pair off the stack pusha e push all does a pushf, then pushes the int e mask1/wsr pair and clears int e mask1 popa e pop all pops the int e mask1/wsr pair and then does a popf interrupts can also not occur immediately after execu- tion of: unimplemented opcodes trap e the software trap instruction signd e the signed prefix for multiply and divide instructions when an interrupt is acknowledged the interrupt pend- ing bit is cleared, and a call is forced to the location indicated by the specified interrupt vector. this call oc- curs after the completion of the instruction in process, except as noted above. the procedure of getting the vector and forcing the call requires 16 state times. if the stack is in external ram an additional 2 state times are required. the maximum number of state times required from the time an interrupt is generated (not acknowledged) until the 80C196KB begins executing code at the desired lo- cation is the time of the longest instruction, norml (normalize e 39 state times), plus the 4 state times prior to the end of the previous instruction, plus the response time (16(internal stack) or 18(external stack) state times). therefore, the maximum response time is 61 (39 a 4 a 18) state times. this does not include the 10 state times required for pushf if it is used as the first instruction in the interrupt routine or additional latency caused by having the interrupt masked or dis- abled. refer to figure 5-5, interrupt response time, to visualize an example of worst case scenario. interrupt latency time can be reduced by careful selec- tion of instructions in areas of code where interrupts are expected. using `ei' followed immediately by a long instruction (e.g. mul, norml, etc.) will in- crease the maximum latency by 4 state times, as an interrupt cannot occur between ei and the instruction following ei. the di, pushf, popf, pusha, popa and trap instructions will also cause the same situa- tion. typically these instructions would only effect la- tency when one interrupt routine is already in process, as these instructions are seldom used at other times. 5.5 interrupt summary many of the interrupt vectors on the 8096bh were shared by multiple interrupts. the interrupts which were shared on the 8096bh are: transmit interrupt, receive interrupt, hsi fifo full, timer2 overflow and extint. on the 80C196KB, each of these inter- rupts have their own interrupt vectors. the source of the interrupt vectors are typically programmed through control registers. these registers can be read in win- dow 15 to determine the source of any interrupt. inter- rupt sources with two possible interrupt vectors, serial receive interrupt sharing serial port and receive inter- rupt vectors for example, should be configured for only one interrupt vector. interrupts with separate vectors include: nmi, trap, unimplemented opcode, timer2 capture, 4th entry into hsi fifo, software timer, hsi.0 pin, high speed outputs, and a/d conversion complete. the nmi, trap and unimplemented opcode interrupts were covered in section 5.0. extint and p0.7 the 80C196KB has two external interrupt vectors; extint (200eh) and extint1 (203ah). the extint vector has two alternate sources selectable by ioc1.1, the external interrupt pin (port 2.2) and port 0.7. the external interrupt pin is the only source for the extint1 interrupt vector. the external interrupt pin should not be programmed to interrupt through both vectors. both external interrupt sources are rising edge triggered. 270651 11 figure 5-5. interrupt response time 32
80C196KB user's guide serial port interrupts the serial port generates one of three possible inter- rupts: transmit interrupt ti(2030h), receive interrupt ri(2032h) and serial(200ch). refer to section 10 for information on the serial port interrupts. the 8096bh shared the ti and ri interrupts on the seri- al interrupt vector. on the 80C196KB, these inter- rupts share both the serial interrupt vector and have their own interrupt vectors. ideally, the transmit and receive interrupts should be programmed as separate interrupt vectors while disabling the serial inter- rupt. for 8096bh compatibility, the interrupts can still use the serial interrupt vector. hsi fifo full and hsi data available hsi fifo full and hsi data available in- terrupts shared the hsi data available inter- rupt vector on the 8096bh. the source of the hsi data available interrupt is controlled by the setting of i/o control register 1,(ioc1.7). setting ioc1.7 to zero will generate an interrupt when a time value is loaded into the holding register. setting the bit to one generates an interrupt when the fifo, indepen- dent of the holding register, has six entries in it. on the 80C196KB, separate interrupt vectors are avail- able for the hsi fifo full(203ch) and hsi data available(2004h) interrupts. the interrupts should be programmed for separate interrupt vector lo- cations. refer to section 8 for more information on the high speed inputs. hsi fifo e 4 the hsi fifo can generate an interrupt when the hsi has four or more entries in the fifo. the hsi fifo e 4 interrupt vectors through location 2034h. refer to section 8 for more information on the high speed in- puts. hsi.0 external interrupt the rising edge on hsi.0 pin can be used as an external interrupt. the hsi.0 pin is sampled during ph1 or clkout low. sampling is guaranteed if the pin is held for at least one state time. the interrupt vectors through location 2008h. the pin does not need to be enabled to the hsi fifo in order to generate the inter- rupt. timer2 and timer1 overflow timer2 and timer1 can interrupt on overflow. these interrupts shared the same interrupt vector timer overflow(2000h) on the 8096bh. the interrupts are individually enabled by setting bits 2 and 3 of ioc1: bit 2 for timer1, and bit 3 for timer2. which timer actually caused the interrupt can be determined by bits 4 and 5 of ios1: bit 4 for timer2 and 5 for timer1. on the 80C196KB timer2 overflow(0h or 8000h) has a separate interrupt vector through location 2038h. timer2 capture the 80C196KB can generate an interrupt in response to a timer2 capture triggered by a rising edge on p2.7. timer2 capture vectors through location 2036h. high speed outputs the high speed outputs interrupt can be generated in response to a programmed hso command which caus- es an external event. hso commands which set or clear the high speed output pins are considered external events. status register ios2 indicates which hso events have occured and can be used to arbitrate which hso command caused the interrupt. the high speed output interrupt vectors indirectly through location 2006h. for more information on high speed outputs, refer to section 9. software timers hso commands which create internal events can inter- rupt through the software timer interrupt vector. in- ternal events include triggering an a/d conversion, re- setting timer2 and software timers. status registers ios2 and ios1 can be used to determine which internal hso event has occured. location 200ah is the inter- rupt vector for the software timer interrupt. refer to section 9 for more information on software timers and the hso. a/d conversion complete the a/d conversion complete interrupt can generate an interrupt in response to a completed a/d conver- sion. the interrupt vectors indirectly through location 2002h. refer to section 11 for more information on the a/d converter. 6.0 pulse width modulation output (d/a) digital to analog conversion can be done with the pulse width modulation output; a block diagram of the cir- cuit is shown in figure 6-1. the 8-bit counter is incre- mented every state time. when it equals 0, the pwm output is set to a one. when the counter matches the value in the pwm register, the output is switched low. when the counter overflows, the output is once again switched high. a typical output waveform is shown in 33
80C196KB user's guide figure 6-2. note that when the pwm register equals 00, the output is always low. additionally, the pwm register will only be reloaded from the temporary latch when the counter overflows. this means the compare circuit will not recognize a new value until the counter has expired preventing missed pwm edges. the 80C196KB pwm unit has a prescaler bit (divide by 2) which is enabled by setting ioc2.2 e 1. the pwm frequencies are shown in figure 6-3. the output waveform is a variable duty cycle pulse which repeats every 256 or 512 state times (42.75 m s or 85.5 m sat 12 mhz). changes in the duty cycle are made by writ- ing to the pwm register at location 17h. the value programmed into the pwm register can be read in window 15 (wsr e 15). there are several types of mo- tors which require a pwm waveform for more efficient operation. additionally, if this waveform is integrated it will produce a dc level which can be changed in 256 steps by varying the duty cycle. as described in the next section. xtal1 e 8 mhz 10 mhz 12 mhz ioc2.2 e 0 15.6 khz 19.6 khz 23.6 khz ioc2.2 e 1 7.8 khz 9.8 khz 11.8 khz figure 6-3. pwm frequencies the pwm output shares a pin with port 2, pin 5 so that these two features cannot be used at the same time. ioc1.0 equal to 1 selects the pwm function instead of the standard port function. 270651 12 # duty cycle programmable in 256 steps figure 6-1. pwm block diagram 270651 13 figure 6-2. typical pwm outputs 34
80C196KB user's guide 6.1 analog outputs analog outputs can be generated by two methods, ei- ther by using the pwm output or the hso. see section 9.7 for information on generating a pwm with the high speed output unit. either device will generate a rectangular pulse train that varies in duty cycle and period. if a smooth analog signal is desired as an out- put, the rectangular waveform must be filtered. in most cases this filtering is best done after the signal is buffered to make it swing from 0 to 5 volts since both of the outputs are guaranteed only to low current lev- els. a block diagram of the type of circuit needed is shown in figure 6-4. by proper selection of compo- nents, accounting for temperature and power supply drift, a highly accurate 8-bit d to a converter can be made using either the hso or the pwm output. figure 6-5 shows two typical circuits. if the hso is used the accuracy could be theoretically extended to 16-bits, however the temperature and noise related problems would be extremely hard to handle. when driving some circuits it may be desirable to use unfiltered pulse width modulation. this is particularly true for motor drive circuits. the pwm output can generate these waveforms if a fixed period on the order of 64 m s is acceptable. if this is not the case then the hso unit can be used. the hso can generate a vari- able waveform with a duty cycle variable in up to 65536 steps and a period of up to 87.5 milliseconds. both of these outputs produce chmos levels. 270651 14 figure 6-4. d/a buffer block diagram 270651 15 270651 16 figure 6-5. buffer circuits for d/a 35
80C196KB user's guide 7.0 timers 7.1 timer1 timer1 is a 16-bit free-running timer which is incre- mented every eight state times. an interrupt can be generated in response to an overflow. it is read through location 0ah in window 0 and written in window 15. figure 7-1 shows a block diagram of the timers. care must be taken when writing to it if the high speed i/o (hsio) subsystem is being used. hso time entries in the cam depend on exact matches with timer1. writes to timer1 should be taken into account in soft- ware to ensure events in the hso cam are not missed or occur in an order which may be unexpected. chang- ing timer1 with incoming events on the high speed input lines may corrupt relative references between captured inputs. further information on the high speed outputs and high speed inputs can be found in sections 8 and 9 respectively. 7.2 timer2 timer2 on the 80C196KB can be used as an external reference for the hso unit, an up/down counter, an external event capture or as an extra counter. timer2 is clocked externally using either the t2clk pin (p2.3) or the hsi.1 pin depending on the state of ioc0.7. timer 2 counts both positive and negative transitions. the maximum transition speed is once per state time in the fast increment mode, and once every 8 states oth- erwise. clkout cannot be used directly to clock tim- er2. it must first be divided by 2. timer2 can be read and written through location 0ch in window 0. figure 7-1 shows a block diagram of the timers. timer2 can be reset by hardware, software or the hso unit. either t2rst (p2.4) or hsi.0 can reset timer2 externally depending on the setting of ioc0.5. figure 7-2 shows the configuration and input pins of timer2. figure 7-3 shows the reset and clocking options for timer2. the appropriate control registers can be read in window 15 to determine the programmed modes. however, ioc0.1(t2rst) is not latched and will read a1. caution should be used when writing to the timers if they are used as a reference to the high speed output unit. programmed hso commands could be missed if the timers do not count continuously in one direction. high speed output events based on timer2 must be carefully programmed when using timer2 as an up/down counter or is reset externally. programmed events could be missed or occur in the wrong order. refer to section 9 for more information on using the timers with the high speed output unit. capture register the value in timer2 can be captured into the t2cap- ture register by a rising edge on p2.7. the edge must be held for at least one state time as discussed in the next section. t2cap is located at 0ch in window 15. the interrupt generated by a capture vectors through loca- tion 2036h. fast increment mode timer2 can be programmed to run in fast increment mode to count transitions every state time. setting ioc2.0 programs timer2 in the fast increment mode. in this mode, the events programmed on the hso unit with timer2 as a reference will not execute properly since the hso requires eight state times to compare every location in the hso cam. with timer2 as a reference for the hso unit, timer2 transitioning every state time may cause programmed hso events to be missed. for this reason, timer2 should not be used as a reference for the hso if transitions occur faster than once every eight state times. timer2 should not be reset in the fast increment mode. all timer2 resets are synchronized to an eight state time clock. if timer2 is reset when clocking faster than once every 8 states, it may reset on a different count. up/down counter mode timer2 can be made to count up or down based on the port 2.6 pin if ioc2.1 e 1. however, caution must be used when this feature is working in conjunction with the hso. if timer2 does not complete a full cycle it is possible to have events in the cam which never match the timer. these events would stay in the cam until the cam is cleared or the chip is reset. 7.3 sampling on external timer pins the t2up/dn, t2clk, t2rst, and t2cap pins are sampled during ph1. ph1 roughly corresponds to clkout low externally. for valid sampling, the in- puts should be present 30 nsec prior to the rising edge of clkout or it may not be sampled until the next clkout. if the t2up/dn signal changes and be- comes stable before, or at the same time that the t2clk signal changes, the count will go into the new direction. 36
80C196KB user's guide 270651 5 figure 7-1. timer block diagram bit e 1 bit e 0 ioc0.1 reset timer2 each write no action ioc0.3 enable external reset disable ioc0.5 hsi.0 is ext. reset source t2rst is reset source ioc0.7 hsi.1 is t2 clock source t2clk is clock source ioc1.3 enable timer2 overflow int. disable overflow interrupt ioc2.0 enable fast increment disable fast increment ioc2.1 enable downcount feature disable downcount p2.6 count down if ioc2.1 e 1 count up ioc2.5 interrupt on 7fffh/8000h interrupt on 0ffffh/0000h p2.7 capture timer2 into t2capture on rising edge figure 7-2. timer2 configuration and control pins 270651 17 figure 7-3. timer2 clock and reset options 7.4 timer interrupts both timer1 and timer2 can trigger a timer overflow interrupt and set a flag in the i/o status register 1 (ios1). timer1 overflow is controlled by setting ioc1.2 and the interrupt status is indicated in ios1.5. the timer overflow interrupt is enabled by set- ting int e mask.0. a timer2 overflow condition interrupts through loca- tion 2000h by setting ioc1.3 and setting int e mask.0. alternatively, timer2 overflow can interrupt through location 2038h by setting int e mask1.3. the status of the timer2 overflow interrupt is indicated in ios1.4. interrupts can be generated if timer2 crosses the 0ffffh/0000h boundary or the 7fffh/8000h boundary in either direction. by having two interrupt points it is possible to have interrupts enabled even if 37
80C196KB user's guide timer2 is counting up and down centered around one of the interrupt points. the boundaries used to control the timer2 interrupt is determined by the setting of ioc2.5. when set, timer2 will interrupt on the 7fffh/8000h boundary, otherwise, the 0ffffh/ 0000h boundary interrupts. a t2capture interrupt is enabled by setting int e mask1.3. the interrupt will vector through location 2036h. caution must be used when examining the flags, as any access (including compare and jump on bit) of ios1 clears bits 0 through 5 including the software timer flags. it is, therefore, recommended to copy the byte to a temporary register before testing bits. writing to ios1 in window 15 will set the status bits but not cause interrupts. the general enabling and disabling of the timer interrupts are controlled by the interrupt mask register bit 0. in all cases, setting a bit enables a func- tion, while clearing a bit disables it. 8.0 high speed inputs the high speed input unit (hsi) can record the time an event occurs with respect to timer1. there are 4 lines (hsi.0 through hsi.3) which can be used in this mode and up to a total of 8 events can be recorded. hsi.2 and hsi.3 are bidirectional pins which can also be used as hso.4 and hso.5. the i/o control regis- ters (ioc0 and ioc1) determine the functions of these pins. the values programmed into ioc0 and ioc1 can be read in window 15. a block diagram of the hsi unit is shown in figure 8-1. hsi trigger options 270651 18 270651 19 figure 8-1. high speed input unit hsi status register (hsi e status) 270651 22 figure 8-2. hsi status register diagram 38
80C196KB user's guide when an hsi event occurs, a 7 c 20 fifo stores the 16 bits of timer1, and the 4 bits indicating which pins recorded events associated with that time tag. there- fore, if multiple pins are being used as hsi inputs, soft- ware must check each status bits when processing on hsi event. multiple pins can recognize events with the same time tag. it can take up to 8 state times for this information to reach the holding register. for this rea- son, 8 state times must elapse between consecutive reads of hsi e time. when the fifo is full, one addi- tional event, for a total of 8 events, can be stored by considering the holding register part of the fifo. if the fifo and holding register are full, any additional events will not be recorded. 8.1 hsi modes there are 4 possible modes of operation for each of the hsi pins. the hsi e mode register at location 03h controls which pins will look for what type of events. in window 15, reading the register will read back the pro- grammed hsi mode. the 8-bit register is set up as shown in figure 8-3. 270651 20 figure 8-3. hsi mode register 1 the maximum input speed is 1 event every 8 state times except when the 8 transition mode is used, in which case it is 1 transition per state time. the hsi pins can be individually enabled and disabled using bits in ioc0 as shown in figure 8-4. if the pin is disabled, transitions are not entered in the fifo. how- ever, the input bits of the hsi e status register (fig- ure 8-2) are always valid regardless of whether the pin is enabled to the fifo. this allows the hsi pins to be used as general purpose input pins. 270651 21 figure 8-4. ioc0 control of hsi pin functions 8.2 hsi status bits 6 and 7 of the i/o status register 1 (ios1esee figure 8-5) indicate the status of the hsi fifo. if bit 7 is set, the hsi holding register is loaded. the fifo may or may not contain 1 5 events. if bit 6 is set, the fifo contains 6 entries. if the fifo fills, future events will not be recorded. reading ios1 clears bits 0 5, so keep an image of the register and test the image to retain all 6 bits. reading the hsi holding register must be done in a certain order. the hsi e status register (figure 8- 2) is read first to obtain the status and input bits. sec- ond, the hsi e time register (04h) is read to obtain the time tag. reading hsi e time unloads one level of the fifo. if the hsi e time is read before hsi e status, the contents of hsi e status associ- ated with that hsi e time tag are lost. 270651 23 figure 8-5. i/o status register 1 39
80C196KB user's guide if the hsi e time register is read without the holding register being loaded, the returned value will be indeter- minate. under the same conditions, the four bits in hsi e status indicating which events have occurred will also be indeterminate. the four hsi e status bits which indicate the current state of the pins will always return the correct value. it should be noted that many of the status register con- ditions are changed by a reset, see section 13. writing to hsi e time in window 15 will write to the hsi fifo holding register. writing to hsi e status in window 15 will set the status bits but will not affect the input bits. 8.3 hsi interrupts interrupts can be generated by the hsi unit in three ways: when a value moves from the fifo into the holding register; when the fifo (independent of the holding register) has 4 or more event stored; when the fifo has 6 or more events. the hsi data available and hsi fifo full interrupts are shared on the 8096bh. the source for the hsi data available interrupt is controlled by ioc1.7. when ioc1.7 is cleared, the hsi will gen- erate an interrupt when the holding register is loaded. the interrupt indicates at least one hsi event has oc- curred and is ready to be processed. the interrupt vec- tors through location 2004h. the interrupt is enabled by setting int e mask.2. the generation of a hsi data available interrupt will set ios1.7. the hsi fifo full interrupt will vector through hsi data available if ioc1.7 is set. on the 80C196KB, the hsi fifo full has a separate inter- rupt vector at location 203ch. a hsi fifo full interrupt occurs when the hsi fifo has six or more entries loaded independent of the holding register. since all interrupts are rising edge trig- gered, the processor will not be reinterrupted until the fifo first contains 5 or less records, then contains six or more. the hsi fifo full interrupt mask bit is int e mask1.6. the occurrence of a hsi fifo full interrupt is indicated by ios1.6. earlier warning of a impending fifo full condition can be achieved by the hsi fifo 4th entry interrupt. the hsi e fifo e 4 interrupt generates an interrupt when four or more events are stored in the hsi fifo independent of the holding register. the interrupt is enabled by setting int e mask1.2. the hsi e fifo e 4 vectors indirectly through location 2034h. there is no status flag associated with the hsi e fifo e 4 interrupt since it has its own independent in- terrupt vector. the hsi.0 pin can generate an interrupt on the rising edge even if its not enabled to the hsi fifo. an inter- rupt generated by this pin vectors through location 2008h. 8.4 hsi input sampling the hsi pins are sampled internally once each state time. any value on these pins must remain stable for at least 1 full state time to guarantee that it is recognized. the actual sampling occurs during ph1 or during clkout low. the hsi inputs should be valid at least 30 nsec before the rising of clkout. otherwise, the hsi input may be sampled in the next clkout. therefore, if information is to be synchronized to the hsi it should be latched on the rising edge of clkout. 8.5 initializing the hsi to start the hsi, the following steps and the sequence must be observed; 1) flush the fifo, 2) enable the hsi interrupts, and 3) initialize and enable the hsi pins. the following section of code can be used to flush the fifo: reflush: ld 0, hsi time ;clear an event skip0 ;wait 8 state times skip0 jbs ios1, 7, reflush enabling the hsi pins before enabling the interrupts can cause a fifo lockout condition. for example, if the hsi pins were enabled first, an event could get loaded into the holding register before the hsi e data e available interrupt is enabled. if this happens, no hsi e data e available interrupts will ever occur. 9.0 high speed outputs the high speed output unit (hso) trigger events at specific times with minimal cpu overhead. events are generated by writing commands to the hso e com- mand register and the relative time at which the events are to occur into the hso e time register. in window 15, these registers will read the last value pro- grammed in the holding register. the programmable events include: starting an a/d conversion, resetting timer2, setting 4 software flags, and switching 6 output lines (hso.0 through hso.5). the format of the hso e command register is shown in figure 9-1. commands 0ch and 0dh are reserved for use on fu- ture products. up to eight events can be pending at one time and interrupts can be generated whenever any of these events are triggered. hso.4 and hso.5 are bi- 40
80C196KB user's guide 76543210 hso e cam tmr2/ set/ int/ channel 06h command lock tmr1 clear int cam lock e locks event in cam if this is enabled by ioc2.6 (ena e lock) tmr/tmr1 e events based on timer2/based on timer1 if 0 set/clear e set hso pin/clear hso pin if 0 int/int e cause interrupt/no interrupt if 0 channel: 05: hso pins 0 5 separately (in hex) 6: hso pins 0 and 1 together 7: hso pins 2 and 3 together 8 b: software timers 0 3 c d: unflagged events (do not use for future compatibility) e: reset timer2 f: start a to d conversion figure 9-1. hso command register directional pins which are multiplexed with hsi.2 and hsi.3 respectively. bits 4 and 6 of i/o control regis- ter 1 (ioc1.4, ioc1.6) enable hso.4 and hso.5 as outputs. the control registers can be read in window 15 to determine the programmed modes for the hso. however, the ioc2.7(cam clear) bit is not latched and will read as a one. entries can be locked in the cam to generate periodic events or waveforms. 9.1 hso interrupts and software timers the hso unit can generate two types of interrupts. the high speed output execution interrupt can be generat- ed (if enabled) for hso commands which change one or more of the six output pins. the other hso inter- rupt is the interrupt which can be generated by any other hso command, (e.g. triggering the a/d, reset- ting timer2 or generating a software time delay). hso interrupt status register ios2 at location 17h displays the hso events which have occurred. ios2 is shown in figure 9-2. the events displayed are hso.0 through hso.5, timer2 reset and start of an a/d conversion. ios2 is cleared when accessed, therefore, the register should be saved in an image register if more than one bit is being tested. the status register is useful in determining which events have caused an hso generated interrupt. writ- ing to this register in window 15 will set the status bits but not cause interrupts. in window 15, writing to ios2 can set the high speed output lines to an initial value. refer to section 2.2 for more information on window 15. ios2: 7 6543210 start t2 hso.5 hso.4 hso.3 hso.2 hso.1 hso.0 a/d reset 17h read indicates which hso event occcured start a/d: hso e cmd 15, start a/d t2reset: hso e cmd 14, timer2 reset hso.0 5: output pins hso.0 through hso.5 figure 9-2. i/o status register 2 41
80C196KB user's guide software timers the hso can be programmed to generate interrupts at preset times. up to four such ``software timers'' can be in operation at a time. as each preprogrammed time is reached, the hso unit sets a software timer flag. if the interrupt bit in the hso command register was set then a software timer interrupt will also be generated. the interrupt service routine can then examine i/o status register 1 (ios1) to determine which software timer expired and caused the interrupt. when the hso resets timer2 or starts an a/d conversion, it can also be programmed to generate a software timer interrupt. if more than one software timer interrupt occurs in the same time frame, multiple status bits will be set. each read or test of any bit in ios1 (see figure 9-5) will clear bits 0 through 5. be certain to save the byte before testing it unless you are only concerned with 1 bit. see also section 11.5. 9.2 hso cam a block diagram of the hso unit is shown in figure 9- 3. the content addressable memory (cam) file is the center of control. one cam register is compared with the timer values every state time, taking 8 state times to compare all cam registers with the timers. this de- fines the time resolution of the hso to be 8 state times (1.33 microseconds at an oscillator frequency of 12 mhz). each cam register is 24 bits wide. sixteen bits specify the time at which the action is to be carried out, one bit for the lock bit and 7 bits specify both the nature of the action and whether timer1 or timer2 is the reference. the format of the command to the hso unit is shown in figure 9-1. note that bit 5 is ignored for command channels 8 through 0fh. to enter a command into the cam file, write the 8-bit ``command tag'' into location 0006h followed by the time the action is to be carried out into word address 0004h. the typical code would be: ldb hso command, # what to do add hso time,timer1, # when to do it 270651 24 high speed output controls 6 pins 4 software timers 2 interrupts initiate a/d conversion reset timer2 figure 9-3. high speed output unit 42
80C196KB user's guide 270651 25 figure 9-4. i/o status register 0 writing the time value loads the hso holding register with both the time and the last written command tag. the command does not actually enter the cam file until an empty cam register becomes available. commands in the holding register will not execute even if their time tag is reached. commands must be in the cam to execute. commands in the holding register can also be overwritten. since it can take up to 8 state times for a command to move from the holding register to the cam, 8 states must be allowed between succes- sive writes to the cam. to provide proper synchronization, the minimum time that should be loaded to timer1 is timer1 a 2. small- er values may cause the timer match to occur 65,636 counts later than expected. a similar restriction applies if timer2 is used. care must be taken when writing the command tag for the hso, because an interrupt can occur between writ- ing the command tag and loading the time value. if the interrupt service routine writes to the hso, the com- mand tag used in the interrupt routine will overwrite the command tag from the main routine. one way of avoiding this problem would be to disable interrupts when writing to the hso unit. 9.3 hso status before writing to the hso, it is desirable to ensure that the holding register is empty. if it is not, writing to the hso will overwrite the value in the holding register. i/o status register 0 (ios0) bits 6 and 7 indicate the status of the hso unit. if ios0.6 equals 0, the holding register is empty and at least one cam register is emp- ty. if ios0.7 equals 0, the holding register is empty. the programmer should carefully decide which of these two flags is the best to use for each application. this register also shows the current status of the hso.0 through hso.5. the hso pins can be set by writing to 270651 26 figure 9-5. i/o status register 1 (ios1) this register in window 15. the format for i/o status register 0 is shown in figure 9-4. the expiration of software timer 0 through 4, and the overflow of timer1 and timer2 are indicated in ios1. the status bits can be set in window 15 but not cause interrupts. the register is shown in figure 9-5. whenever the processor reads this register all of the time-related flags (bits 5 through 0) are cleared. this applies not only to explicit reads such as: ldb al,ios1 but also to implicit reads such as: jbs ios1,3,somewhere else which jumps to somewhere e else if bit 3 of ios1 is set. in most cases this situation can best be handled by hav- ing a byte in the register file which maintains an image of the register. any time a hardware timer interrupt or a hso software timer interrupt occurs the byte can be updated: orb ios1 image,ios1 leaving ios1 e image containing all the flags that were set before plus all the new flags that were read and cleared from ios1. any other routine which needs to sample the flags can safely check ios1 e image. note that if these routines need to clear the flags that they have acted on, then the modification of ios1 e image must be done from inside a critical region. 9.4 clearing the hso and locked entries all 8 cam locations of the hso are compared before any action is taken. this allows a pending external 43
80C196KB user's guide event to be cancelled by simply writing the opposite event to the cam. however, once an entry is placed in the cam, it cannot be removed until either the speci- fied timer matches the written value , a chip reset oc- curs or ioc2.7 is set. ioc2.7 is the cam clear bit which clears all entries in the cam. internal events cannot be cleared by writing an oppo- site event. this includes events on hso channels 8 through f. the only method for clearing these events are by a reset or setting ioc2.7. hso locked entries the cam lock bit (hso e command.7) can be set to keep commands in the cam, otherwise the commands will clear from the cam as soon as they cause an event. this feature allows for generation periodic events based on timer2 and must be enabled by setting ioc2.6. to clear locked events from the cam, the en- tire cam can be cleared by writing a one to the cam clear bit ioc2.7. a chip reset will also clear the cam. locked entries are useful in applications requiring peri- odic or repetitive events to occur. timer2 used as an hso reference can generate periodic events with the use of the hso t2rst command. hso events pro- grammed with a hso time less then the timer2 reset time will occur repeatedly as timer2 resets. recurrent software tasks can be scheduled by locking software timers commands into the high speed output unit. continuous sampling of the a/d converter can be ac- compished by programming a locked hso a/d con- version command. one of the most useful features is the generation of multiple pwm's on the high speed output lines. locked entries provide the ability to pro- gram periodic events while minimizing the software overhead. section 9.6 describes the generation of four pwms using locked entries. individual external events setting or clearing an hso pin can by cancelled by writing the opposite event to the cam. the hso events do not occur until the timer reference has changed state. an event programmed to set and clear an hso event at the same time will cancel each other out. locked entries can correspondingly be cancelled using this method. however, the entries re- main in the hso cam and can quickly fill up the available eight locations. as an alternative, all entries in the hso cam can be cleared by setting ioc2.7. 9.5 hso precautions timer1 is incremented once every 8 state-times. when it is being used as the reference timer for an hso com- mand, the comparator has a chance to look at all 8 cam registers before timer1 changes its value. writ- ing to timer1, which is allowed in window 15, should be carefully done. the user should ensure writing to timer1 will not cause programmed hso events to be missed or occur in the wrong order. the same precau- tion applies to timer2. the hso requires at least eight state times to compare each entry in the cam. therefore, the fast increment mode for timer2 cannot be used as a reference for the hso if transitions occur faster then once every eight state times. referencing events when timer2 is being used as an up/down counter could cause events to occur in oppo- site order or be missed entirely. additionally, locked entries could possibly occur several times if timer2 is oscillating around the time tag for an entry. when using timer2 as the hso reference, caution must be taken that timer2 is not reset prior to the highest value for a timer2 match in the cam. if that match is never reached, the event will remain pending in the cam until the part is reset or cam is cleared. 9.6 pwm using the hso the hso unit can generate pwm waveforms with very little cpu overhead using timer2 as a reference. a pwm is generated by programming an hso line to a high and a t2rst to occur at the same time. an hso low time is programmed on the cam to generate the duty cycle of the pwm. a repetitive pwm waveform is generated by locking the commands into the cam. re- programming of the duty cycle or pwm frequency can be accomplished by generating a software interrupt and reprogramming the hso high, hso low and t2rst commands. multiple pwms can be programmed using timer2 as a reference and locked cam entries. up to four pwm's can be generated by locking a pwm(high) and pwm(low) into the cam for each hso.0 through hso.3. timer2 is used as a reference and set to zero by programming a t2rst command at the same time an hso command sets all the lines high. two cam en- tries program the four pwm (high) times by setting hso.0/hso.1 and hso.2/hso.3 high with the same command. four entries in the cam set each of the hso lines low. one entry is used to reset timer2. this method uses a total of seven cam entries with little or no software overhead. the pwms can change their duty cycle by reprogramming the cam with different hso levels. changing the duty cycle for each pwm requires the flushing of the cam and reprogramming of all seven entries in the cam. the 80C196KB can flush the en- tire cam by setting bit 7 in the ioc2 register (location 16h). each hso(high) and hso(low) times should be 44
80C196KB user's guide reprogrammed in addition to the timer2 reset com- mand. this method provides for up to four pwm's with no software overhead except when reprogramming the duty cycle of any particular pwm. the code to generate these pwms is shown in figure 9-6. 9.7 hso output timing changes in the hso lines are synchronized to either timer1 or timer2. all of the external hso lines due to change at a certain value of a timer will change just after the incrementing of the timer. internally, the tim- er changes every eight state times during phase1. from an external perspective the hso pin should change just prior to the falling edge of clkout and be stable by its rising edge. information from the hso can be latched on the clkout rising edge. internal events also occur when the reference timer increments. 10.0 serial port the serial port on the 80C196KB has one synchronous and 3 asynchronous modes. the asynchronous modes $include (reg196.inc) ; ********************************************************** ; * ; * generation of four pwm's using locked entries * ; * ; * timer2 is used as a reference and is clocked * ; * externally by t2clk. the high speed outputs are * ; * used as pwms by programming each individual * ; * pwm(low) and pwm(high) time as a locked entry. * ; * the period of the pwm is programmed by resetting * ; * timer2 and setting all the hso lines high at the * ; * same time. the pwms are reprogrammed by * ; * clearing the hso cam and reloading new values * ; * for the pwm period and duty cycle. * ; * ; ********************************************************** rseg at 60h pwm0timl: dsw 1 pwm1timl: dsw 1 pwm2timl: dsw 1 pwm3timl: dsw 1 pwm period: dsw 1 temp: dsw 1 cseg at 2080h ld sp, # 0d0h ; initialize stack pointer ld pwm period, # 0f000h ; intialize pwm period ld pwm0timl, # 2000h ; initialize pwm 0-3 duty cycle ld pwm1timl, # 4000h ld pwm2timl, # 6000h ld pwm3timl, # 8000h ldb ioc2, # 40h ; enable locked entries ldb ioc0, # 0h ; enable t2clk for timer2 clock ; source call pwm program ; program pwm's on cam here: sjmp here ; loop forever figure 9-6. generating four pwms using locked entries 45
80C196KB user's guide pwm program: ldb ioc2, # 0c0h ; flush entire cam ldb hso command, # 0ceh ; program timer2 reset time ld hso time,pwm period nop ; delay eight state times before nop ; next load nop nop ldb hso command, # 0e6h ; hso 0/1 high, locked, timer2 as ; reference ld hso time,pwm period ; set hso high on t2rst nop nop nop nop ldb hso command, # 0e7h ; hso 2/3 high, locked, timer2 ; as reference ld hso time,pwm period ; set hso high on t2rst nop nop nop nop ldb hso command, # 0c0h ; set hso.0 low, locked, timer2 ; as reference ld hso time,pwm0timl ; hso.0 time low nop nop nop nop ldb hso command, # 0c1h ; set hso.1 low, locked, timer2 ; reference ld hso time,pwm1timl ; hso.1 time low nop nop nop nop ldb hso command, # 0c2h ; set hso.2 low, locked,timer2 ; as reference ld hso time,pwm2timl ; hso.2 time low nop nop nop nop ldb hso command, # 0c3h ; set hso.3 low, locked,timer2 ; as reference ld hso time,pwm3timl ; hso.3 time low ret end figure 9-6. generating four pwms using locked entries (continued) 46
80C196KB user's guide are full duplex, meaning they can transmit and receive at the same time. the receiver is double buffered so that the reception of a second byte can begin before the first byte has been read. the transmitter on the 80C196KB is also double buffered allowing continuous transmis- sions. the port is functionally compatible with the seri- al port on the mcs-51 family of microcontrollers, al- though the software controlling the ports is different. data to and from the serial port is transferred through sbuf(rx) and sbuf(tx), both located at 07h. sbuf(tx) holds data ready for transmission and sbuf(rx) contains data received by the serial port. sbuf(tx) and sbuf(rx) can be read and can be written in window 15. mode 0, the synchronous shift register mode, is de- signed to expand i/o over a serial line. mode 1 is the standard 8 bit data asynchronous mode used for normal serial communications. modes 2 and 3 are 9 bit data asynchronous modes typically used for interprocessor communications. mode 2 provides monitoring of a communication line fo ra1inthe9thbit position before causing an interrupt. mode 3 causes interrupts indepen- dant of the 9th bit value. 10.1 serial port status and control control of the serial port is done through the serial port control (sp e con) register shown in figure 10- 1. writing to location 11h accesses sp e con while reading it accesses sp e stat. the upper 3 bits of sp e con must be written as 0s for future compatibil- ity. on the 80C196KB the sp e stat register contains new bits to indicate receive overrun error (oe), fram- ing error (fe), and transmitter empty (txe). the bits which were also present on the 8096bh are the transmit interrupt (ti) bit, the receive interrupt (ri) bit, and the received bit 8 (rb8) or receive parity error (rpe) bit. sp e stat is read-only in window 0 and is shown in figure 10-1. in all modes, the ri flag is set after the last data bit is sampled, approximately in the middle of a bit time. data is held in the receive shift register until the last data bit is received, then the data byte is loaded into sbuf (rx). the receiver on the 80C196KB also checks for a valid stop bit. if a stop bit is not found within the appropriate time, the framing error (fe) bit is set. since the receiver is double-buffered, reception on a second data byte can begin before the first byte is read. however, if data in the shift register is loaded into sbuf (rx) before the previous byte is read, the over- flow error (oe) bit is set. regardless, the data in sbuf (rx) will always be the latest byte received; it will nev- er be a combination of the two bytes. the ri, fe, and oe flags are cleared when sp e stat is read. howev- er, ri does not have to be cleared for the serial port to receive data. sp e con: 7 6 5 4 3 2 1 0 x x x tb8 ren pen m2 m1 11h tb8 e sets the ninth data bit for transmission. cleared after each transmission. not valid if parity is enabled. ren e enables the receiver pen e enables the parity function (even parity) m2, m1 e sets the mode. mode0 e 00, mode1 e 01, mode2 e 10, mode3 e 11 sp e stat 7 6 5 4 3 2 1 0 rb8/ ri ti fe txe oe x x 11h rpe rb8 e set if the 9th data bit is high on reception (parity disabled) rpe e set if parity is enabled and a parity error occurred ri e set after the last data bit is sampled ti e set at the beginning of the stop bit transmission fe e set if no stop bit is found at the end of a reception txe e set if two bytes can be transmitted oe e set if the receiver buffer is overwritten figure 10-1. serial port control and status registers 47
80C196KB user's guide the transmitter empty (txe) bit is set if the transmit buffer is empty and ready to take up to two characters. txe gets cleared as soon as a byte is written to sbuf. two bytes may be written consecutively to sbuf if txe is set. one byte may be written if ti alone is set. by definition, if txe has just been set, a transmission has completed and ti will be set. the ti bit is reset when the cpu reads the sp e stat registers. the tb8 bit is cleared after each transmission and both ti and ri are cleared when sp e stat read. the ri and ti status bits can be set by writing to sp e stat in window 15 but they will not cause an interrupt. read- ing of sp e con in window 15 will read the last value written. whenever the txd pin is used for the serial port it must be enabled by setting ioc1.5 to a 1. i/o control register 1 can be read in window 15 to deter- mine the setting. starting transmissions and receptions in mode 0, if ren e 0, writing to sbuf (tx) will start a transmission. causing a rising edge on ren, or clearing ri with ren e 1, will start a reception. set- ting ren e 0 will stop a reception in progress and inhibit further receptions. to avoid a partial or com- plete undesired reception, ren must be set to zero be- fore ri is cleared. this can be handled in an interrupt environment by using software flags or in straight-line code by using the interrupt pending register to signal the completion of a reception. in the asynchronous modes, writing to sbuf (tx) starts a transmission. a falling edge on rxd will begin a reception if ren is set to 1. new data placed in sbuf (tx) is held and will not be transmitted until the end of the stop bit has been sent. in all modes, the ri flag is set after the last data bit is sampled approximately in the middle of the bit time. also for all modes, the ti flag is set after the last data bit (either 8 th or 9 th ) is sent, also in the middle of the bit time. the flags clear when sp e stat is read, but do not have to be clear for the port to receive or trans- mit. the serial port interrupt bit is set as a logical or of the ri and ti bits. note that changing modes will reset the serial port and abort any transmission or re- ception in progress on the channel. baud rates baud rates are generated based on either the t2clk pin or xtal1 pin. the values used are different than those used for the 8096bh because the 80C196KB uses a divide-by-2 clock instead of a divide-by-3 clock to generate the internal timings. baud rates are calculated using the following formulas where baud e reg is the value loaded into the baud rate register: asynchronous modes 1, 2 and 3: baud e reg e xtal1 baud rate * 16 b 1or t2clk baud rate * 8 synchronous mode 0: baud e reg e xtal1 baud rate * 2 b 1or t2clk baud rate the most significant bit in the baud register value is set to a one to select xtal1 as the source. if it is a zero the t2clk pin becomes the source. the following ta- ble shows some typical baud rate values. baud rates and baud register values baud xtal1 frequency rate 8.0 mhz 10.0 mhz 12.0 mhz 300 1666 / b 0.02 2082 / 0.02 2499 / 0.00 1200 416 / b 0.08 520 / b 0.03 624 / 0.00 2400 207 / 0.16 259 / 0.16 312 / b 0.16 4800 103 / 0.16 129 / 0.16 155 / 0.16 9600 51 / 0.16 64 / 0.16 77 / 0.16 19.2k 25 / 0.16 32 / 1.40 38 / 0.16 baud register valu e / % error a maximum baud rate of 750 kbaud is available in the asynchronous modes with 12 mhz on xtal1. the synchronous mode has a maximum rate of 3.0 mbaud with a 12 mhz clock. location 0eh is the baud regis- ter. it is loaded sequentially in two bytes, with the low byte being loaded first. this register may not be loaded with zero in serial port mode 0. 48
80C196KB user's guide 10.2 serial port interrupts the serial port generates one of three possible inter- rupts: transmit interrupt ti(2030h), receive inter- rupt ri(2032h) and serial(200ch). when the ri bit gets set an interrupt is generated through either 200ch or 2032h depending on which interrupt is en- abled. int e mask1.1 controls the serial port receive interrupt through location 2032h and int e mask.6 controls serial port interrupts through location 200ch. the 8096bh shared the ti and ri interrupts on the serial interrupt vector. on the 80C196KB, these in- terrupts share both the serial interrupt vector and have their own interrupt vectors. when the ti bit is set it can cause an interrupt through the vectors at locations 200ch or 2030. interrupt through location 2030 is determined by int e mask1.0. interrupts through the serial interrupt is controlled by the same bit as the ri interrupt(int e mask.6). the user should not mask off the serial port interrupt when using the double-buffered feature of the transmitter, as it could cause a missed count in the number of bytes being transmitted. 10.3 serial port modes mode 0 mode 0 is a synchronous mode which is commonly used for shift register based i/o expansion. in this mode the txd pin outputs a set of 8 pulses while the rxd pin either transmits or receives data. data is transferred 8 bits at a time with the lsb first. a dia- gram of the relative timing of these signals is shown in figure 10-2. note that this is the only mode which uses rxd as an output. mode 0 timings in mode 0, the txd pin sends out a clock train, while the rxd pin transmits or receives the data. figure 10- 2 shows the waveforms and timing. in this mode the serial port expands the i/o capability of the 80C196KB by simply adding shift registers. a schematic of a typical circuit is shown in figure 10-3. this circuit inverts the data coming in, so it must be reinverted in software. mode 1 mode 1 is the standard asynchronous communications mode. the data frame used in this mode is shown in figure 10-4. it consists of 10 bits; a start bit (0), 8 data bits (lsb first), and a stop bit (1). if parity is enabled by setting spcon.2, an even parity bit is sent instead of the 8th data bit and parity is checked on reception. 270651 28 figure 10-2. mode 0 timing 49
80C196KB user's guide 270651 29 figure 10-3. typical shift register circuit 270651 30 270651 31 figure 10-4. serial port frames, mode 1, 2, and 3 the transmit and receive functions are controlled by separate shift clocks. the transmit shift clock starts when the baud rate generator is initialized, the receive shift clock is reset when a `1 to 0' transition (start bit) is received. the transmit clock may therefore not be in sync with the receive clock, although they will both be at the same frequency. the ti (transmit interrupt) and ri (receive inter- rupt) flags are set to indicate when operations are com- plete. ti is set when the last data bit of the message has been sent, not when the stop bit is sent. if an attempt to send another byte is made before the stop bit is sent the port will hold off transmission until the stop bit is com- plete. ri is set when 8 data bits are received, not when the stop bit is received. note that when the serial port status register is read both ti and ri are cleared. caution should be used when using the serial port to connect more than two devices in half-duplex, (i.e. one wire for transmit and receive). if the receiving proces- sor does not wait for one bit time after ri is set before starting to transmit, the stop bit on the link could be corrupted. this could cause a problem for other devices listening on the link. 50
80C196KB user's guide mode 2 mode 2 is the asynchronous 9th bit recognition mode. this mode is commonly used with mode 3 for multi- processor communications. figure 10-4 shows the data frame used in this mode. it consists of a start bit (0), 9 data bits (lsb first), and a stop bit (1). when transmit- ting, the 9th bit can be set to a one by setting the tb8 bit in the control register before writing to sbuf (tx). the tb8 bit is cleared on every transmission, so it must be set prior to writing to sbuf (tx). during recep- tion, the serial port interrupt and the receive interrupt will not occur unless the 9th bit being received is set. this provides an easy way to have selective reception on a data link. parity cannot be enabled in this mode. mode 3 mode 3 is the asynchronous 9th bit mode. the data frame for this mode is identical to that of mode 2. the transmission differences between mode 3 and mode 2 are that parity can be enabled (pen e 1) and cause the 9th data bit to take the even parity value. the tb8 bit can still be used if parity is not enabled (pen e 0). when in mode 3, a reception always causes an inter- rupt, regardless of the state of the 9th bit. the 9th bit is stored if pen e 0 and can be read in bit rb8. if pen e 1 then rb8 becomes the receive parity error (rpe) flag. mode 2 and 3 timings modes 2 and 3 operate in a manner similar to that of mode 1. the only difference is that the data is now made up of 9 bits, so 11-bit packages are transmitted and received. this means that ti and ri will be set on the 9th data bit rather than the 8th. the 9th bit can be used for parity or multiple processor communications. 10.4 multiprocessor communications mode 2 and 3 are provided for multiprocessor commu- nications. in mode 2 if the received 9th data bit is zero, the ri bit is not set and will not cause an interrupt. in mode 3, the ri bit is set and always causes an interrupt regardless of the value in the 9th bit. the way to use this feature in multiprocessor systems is described be- low. the master processor is set to mode 3 so it always gets interrupts from serial receptions. the slaves are set in mode 2 so they only have receive interrupts if the 9th bit is set. two types of frames are used: address frames which have the 9th bit set and data frames which have the 9th bit cleared. when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address frame which identifies the target slave. slaves in mode 2 will not be interrupted by a data frame, but an address frame will interrupt all slaves. each slave can examine the received byte and see if it is being addressed. the addressed slave switches to mode 3 to receive the coming data frames, while the slaves that were not addressed stay in mode 2 continue exe- cuting. 11.0 a/d converter analog inputs to the 80C196KB system are handled by the a/d converter system. as shown in figure 11-4, the converter system has an 8 channel multiplex- er, a sample-and-hold, and a 10 bit successive approxi- mation a/d converter. conversions can be performed on one of eight channels, the inputs of which share pins with port 0. a conversion can be done in as little as 91 state times. conversions are started by loading the ad e com- mand register at location 02h with the channel num- ber. the conversion can be started immediately by set- ting the go bit to a one. if it is cleared the conversion will start when the hso unit triggers it. the a/d com- mand register must be written to for each conversion, even if the hso is used as the trigger. the result of the conversion is read in the ad e result(high) and ad e result(low) registers. the ad e re- sult(high) contains the most significant eight bits of the conversion. the ad e result(low) register con- tains the remaining two bits and the a/d channel num- ber and a/d status. the format for the ad e com- mand register is shown in figure 11-1. in window 15, reading the ad e command register will read the last command written. writing to the ad e re- sult register will write a value into the result register. 270651 33 figure 11-1. a/d command register 51
80C196KB user's guide the a/d converter can cause an interrupt through the vector at location 2002h when it completes a conver- sion. it is also possible to use a polling method by checking the status (s) bit in the lower byte of the ad e result register, also at location 02h. the status bit will b e a 1 while a conversion is in progress. it takes 8 state times to set this bit after a conversion is 270651 32 figure 11-2. a/d result lo register started. the upper byte of the result register contains the most significant 8 bits of the conversion. the lower byte format is shown in figure 11-2. at high crystal frequencies, more time is needed to al- low the comparator to settle. for this reason ioc2.4 is provided to adjust the speed of the a/d conversion by disabling/enabling a clock prescaler. a summary of the conversion time for the two options is shown below. the numbers represent the number of state times required for conversion, e.g., 91 states is 22.7 m s with an 8 mhz xtal1 (providing a 250 ns state time.) clock prescaler on clock prescaler off ioc2.4 e 0 ioc2.4 e 1 158 states 91 states 26.33 m s @ 12 mhz 22.75 m s @ 8 mhz. figure 11-3. a/d conversion times 270651 34 figure 11-4. a/d converter block diagram 52
80C196KB user's guide 11.1 a/d conversion process the conversion process is initiated by the execution of hso command 0fh, or by writing a one to the go bit in the a/d control register. either activity causes a start conversion signal to be sent to the a/d converter control logic. if an hso command was used, the con- version process will begin when timer1 increments. this aids applications attempting to approach spectral- ly pure sampling, since successive samples spaced by equal timer1 delays will occur with a variance of about g 50 ns (assuming a stable clock on xtal1). howev- er, conversions initiated by writing a one to the ad- con register go bit will start within three state times after the instruction has completed execution resulting in a variance of about 0.50 m s (xtal1 e 12 mhz). once the a/d unit receives a start conversion signal, there is a one state time delay before sampling (sample delay) while the successive approximation register is reset and the proper multiplexer channel is selected. after the sample delay, the multiplexer output is con- nected to the sample capacitor and remains connected for 8 state times in fast mode or 15 state times for slow mode (sample time). after this 8/15 state time ``sam- ple window'' closes, the input to the sample capacitor is disconnected from the multiplexer so that changes on the input pin will not alter the stored charge while the conversion is in progress. the comparator is then auto- zeroed and the conversion begins. the sample delay and sample time uncertainties are each approximately g 50 ns, independent of clock speed. to perform the actual analog-to-digital conversion the 80C196KB implements a successive approximation al- gorithm. the converter hardware consists of a 256-re- sistor ladder, a comparator, coupling capacitors and a 10-bit successive approximation register (sar) with logic that guides the process. the resistor ladder pro- vides 20 mv steps (v ref e 5.12v), while capacitive coupling creates 5 mv steps within the 20 mv ladder voltages. therefore, 1024 internal reference voltages are available for comparison against the analog input to generate a 10-bit conversion result. a successive approximation conversion is performed by comparing a sequence of reference voltages, to the ana- log input, in a binary search for the reference voltage that most closely matches the input. the (/2 full scale reference voltage is the first tested. this corresponds to a 10-bit result where the most significant bit is zero, and all other bits are ones (0111.1111.11b). if the ana- log input was less than the test voltage, bit 10 of the sar is left a zero, and a new test voltage of (/4 full scale (0011.1111.11b) is tried. if this test voltage was lower than the analog input, bit 9 of the sar is set and bit 8 is cleared for the next test (0101.1111.11b). this binary search continues until 10 tests have occurred, at which time the valid 10-bit conversion result resides in the sar where it can be read by software. the total number of state times required for a conver- sion is determined by the setting of ioc2.4 clock pre- scaler bit. with the bit set the conversion time is 91 states and 158 states when the bit is cleared. 11.2 a/d interface suggestions the external interface circuitry to an analog input is highly dependent upon the application, and can impact converter characteristics. in the external circuit's de- sign, important factors such as input pin leakage, sam- ple capacitor size and multiplexer series resistance from the input pin to the sample capacitor must be consid- ered. for the 80C196KB, these factors are idealized in fig- ure 11-5. the external input circuit must be able to charge a sample capacitor (c s ) through a series resist- ance (r i ) to an accurate voltage given a d.c. leakage (i l ). on the 80C196KB, c s is around 2 pf, r i is around 5 k x and i l is specified as 3 m a maximum. in determining the necessary source impedance r s , the value of v bias is not important. 270651 35 figure 11-5. idealized a/d sampling circuitry external circuits with source impedances of 1 k x or less will be able to maintain an input voltage within a tolerance of about g 0.61 lsb (1.0 k x c 3.0 m a e 3.0 mv) given the d.c. leakage. source impedances above 2 k x can result in an external error of at least one lsb due to the voltage drop caused by the 3 m a leakage. in addition, source impedances above 25 k x may degrade converter accuracy as a result of the inter- nal sample capacitor not being fully charged during the 1 m s (12 mhz clock) sample window. if large source impedances degrade converter accuracy because the sample capacitor is not charged during the sample time, an external capacitor connected to the pin compensates for this. since the sample capacitor is 2 pf, a 0.005 m f capacitor (2048 * 2 pf) will charge the sample capacitor to an accurate input voltage of g 0.5 lsb. an external capacitor does not compensate for the voltage drop across the source resistance, but charges the sample capacitor fully during the sample time. 53
80C196KB user's guide placing an external capacitor on each analog input will also reduce the sensitivity to noise, as the capacitor combines with series resistance in the external circuit to form a low-pass filter. in practice, one should include a small series resistance prior to the external capacitor on the analog input pin and choose the largest capacitor value practical, given the frequency of the signal being converted. this provides a low-pass filter on the input, while the resistor will also limit input current during over-voltage conditions. figure 11-6 shows a simple analog interface circuit based upon the discussion above. the circuit in the fig- ure also provides limited protection against over-volt- age conditions on the analog input. should the input voltage inappropriately drop significantly below ground, diode d2 will forward bias at about 0.8 dcv. since the specification of the pin has an absolute maxi- mum low voltage of b 0.3v, this will leave about 0.5v across the 270 x resistor, or about 2 ma of current. this should limit the current to a safe amount. however, before any circuit is used in an actual applica- tion, it should be thoroughly analyzed for applicability to the specific problem at hand. 270651 36 figure 11-6. suggested a/d input circuit analog references reference supply levels strongly influence the absolute accuracy of the conversion. for this reason, it is recom- mended that the angnd pin be tied to the two v ss pins at the power supply. bypass capacitors should also be used between v ref and angnd. angnd should be within about a tenth of a volt of v ss .v ref should be well regulated and used only for the a/d converter. the v ref supply can be between 4.5v and 5.5v and needs to be able to source around 5 ma. see section 13 for the minimum hardware connections. note that if only ratiometric information is desired, v ref can be connected to v cc . in addition, v ref and angnd must be connected even if the a/d converter is not being used. remember that port 0 receives its power from the v ref and angnd pins even when it is used as digital i/o. 11.3 the a/d transfer function the conversion result is a 10-bit ratiometric representa- tion of the input voltage, so the numerical value ob- tained from the conversion will be: int [ 1023 c (v in b angnd)/(v ref b angnd) ] . this produces a stair-stepped transfer function when the output code is plotted versus input voltage (see fig- ure 11-7). the resulting digital codes can be taken as simple ratiometric information, or they provide infor- mation about absolute voltages or relative voltage changes on the inputs. the more demanding the appli- cation is on the a/d converter, the more important it is to fully understand the converter's operation. for simple applications, knowing the absolute error of the converter is sufficient. however, closing a servo-loop with analog inputs necessitates a detailed understand- ing of an a/d converter's operation and errors. the errors inherent in an analog-to-digital conversion process are many: quantizing error, zero offset, full- scale error, differential non-linearity, and non-linearity. these are ``transfer function'' errors related to the a/d converter. in addition, converter temperature drift, v cc rejection, sample-hold feedthrough, multiplexer off-isolation, channel-to-channel matching and random noise should be considered. fortunately, one ``absolute error'' specification is available which describes the sum total of all deviations between the actual conver- sion process and an ideal converter. however, the vari- ous sub-components of error are important in many applications. these error components are described in section 11.5 and in the text below where ideal and actu- al converters are compared. an unavoidable error simply results from the conver- sion of a continuous voltage to an integer digital repre- sentation. this error is called quantizing error, and is always g 0.5 lsb. quantizing error is the only error seen in a perfect a/d converter, and is obviously pres- ent in actual converters. figure 11-7 shows the transfer function for an ideal 3-bit a/d converter (i.e. the ideal characteristic). note that in figure 11-7 the ideal characteristic pos- sesses unique qualities: it's first code transition occurs when the input voltage is 0.5 lsb; it's full-scale code transition occurs when the input voltage equals the full- 54
80C196KB user's guide figure 11-7. ideal a/d characteristic 270651 37 55
80C196KB user's guide figure 11-8. actual and ideal characteristics 270651 38 56
80C196KB user's guide figure 11-9. terminal based characteristic 270651 39 57
80C196KB user's guide scale reference minus 1.5 lsb; and it's code widths are all exactly one lsb. these qualities result in a digitiza- tion without offset, full-scale or linearity errors. in oth- er words, a perfect conversion. figure 11-8 shows an actual characteristic of a hypo- thetical 3-bit converter, which is not perfect. when the ideal characteristic is overlaid with the imperfect char- acteristic, the actual converter is seen to exhibit errors in the location of the first and final code transitions and code widths. the deviation of the first code transition from ideal is called ``zero offset'', and the deviation of the final code transition from ideal is ``full-scale error''. the deviation of the code widths from ideal causes two types of errors. differential non-linearity and non- linearity. differential non-linearity is a local linearity error measurement, whereas non-linearity is an over- all linearity error measure. differential non-linearity is the degree to which actual code widths differ from the ideal one lsb width. it gives the user a measure of how much the input voltage may have changed in order to produce a one count change in the conversion result. non-linearity is the worst case deviation of code transitions from the corre- sponding code transitions of the ideal characteristic. non-linearity describes how much differential non- linearities could add up to produce an overall maxi- mum departure from a linear characteristic. if the dif- ferential non-linearity errors are too large, it is possi- ble for an a/d converter to miss codes or exhibit non- monotonicity. neither behavior is desirable in a closed- loop system. a converter has no missed codes if there exists for each output code a unique input voltage range that produces that code only. a converter is monotonic if every subsequent code change represents an input voltage change in the same direction. differential non-linearity and non-linearity are quantified by measuring the terminal based linearity errors. a terminal based characteristic results when an actual characteristic is shifted and rotated to elimi- nate zero offset and full-scale error (see figure 11-9). the terminal based characteristic is similar to the ac- tual characteristic that would be seen if zero offset and full-scale error were externally trimmed away. in prac- tice, this is done by using input circuits which include gain and offset trimming. in addition, v ref on the 80C196KB could also be closely regulated and trimmed within the specified range to affect full-scale error. other factors that affect a real a/d converter system include sensitivity to temperature, failure to completely reject all unwanted signals, multiplexer channel dissim- ilarities and random noise. fortunately these effects are small. temperature sensitivities are described by the rate at which typical specifications change with a change in temperature. undesired signals come from three main sources. first, noise on v cc ev cc rejection. second, input signal changes on the channel being converted after the sam- ple window has closedefeedthrough. third, signals applied to channels not selected by the multiplexere off-isolation. finally, multiplexer on-channel resistances differ slight- ly from one channel to the next causing channel-to- channel matching errors, and random noise in general results in repeatability errors. 11.4 a/d glossary of terms figures 11-7, 11-8, and 11-9 display many of these terms. refer to ap-406 `mcs-96 analog acquisition primer` for additional information on the a/d terms. absolute error ethe maximum difference be- tween corresponding actual and ideal code transitions. absolute error accounts for all deviations of an actual converter from an ideal converter. actual characteristic ethe characteristic of an actual converter. the characteristic of a given con- verter may vary over temperature, supply voltage, and frequency conditions. an actual characteristic rarely has ideal first and last transition locations or ideal code widths. it may even vary over multiple conversion un- der the same conditions. break-before-make ethe property of a multi- plexer which guarantees that a previously selected channel will be deselected before a new channel is se- lected. (e.g. the converter will not short inputs togeth- er.) channel-to-channel matching ethe dif- ference between corresponding code transitions of actu- al characteristics taken from different channels under the same temperature, voltage and frequency condi- tions. characteristic ea graph of input voltage ver- sus the resultant output code for an a/d converter. it describes the transfer function of the a/d converter. code ethe digital value output by the converter. code center ethe voltage corresponding to the midpoint between two adjacent code transitions. code transition ethe point at which the con- verter changes from an output code of q, to a code of q a 1. the input voltage corresponding to a code tran- sition is defined to be that voltage which is equally like- ly to produce either of two adjacent codes. code width ethe voltage corresponding to the difference between two adjacent code transitions. 58
80C196KB user's guide crosstalk esee ``off-isolation''. d.c. input leakage eleakage current to ground from an analog input pin. differential non-linearity ethe differ- ence between the ideal and actual code widths of the terminal based characteristic of a converter. feedthrough eattenuation of a voltage applied on the selected channel of the a/d converter after the sample window closes. full scale error ethe difference between the expected and actual input voltage corresponding to the full scale code transition. ideal characteristic ea characteristic with its first code transition at v in e 0.5 lsb, its last code transition at v in e (v ref b 1.5 lsb) and all code widths equal to one lsb. input resistance ethe effective series resistance from the analog input pin to the sample capacitor. lsbeleast significant bit : the voltage value corresponding to the full scale voltage divided by 2 n , where n is the number of bits of resolution of the con- verter. for a 10-bit converter with a reference voltage of 5.12 volts, one lsb is 5.0 mv. note that this is different than digital lsbs, since an uncertainty of two lsbs, when referring to an a/d converter, equals 10 mv. (this has been confused with an uncertainty of two digital bits, which would mean four counts, or 20 mv.) monotonic ethe property of successive approxi- mation converters which guarantees that increasing in- put voltages produce adjacent codes of increasing value, and that decreasing input voltages produce adjacent codes of decreasing value. no missed codes efor each and every output code, there exists a unique input voltage range which produces that code only. non-linearity ethe maximum deviation of code transitions of the terminal based characteristic from the corresponding code transitions of the ideal characteris- tics. off-isolation eattenuation of a voltage applied on a deselected channel of the a/d converter. (also referred to as crosstalk.) repeatability ethe difference between corre- sponding code transitions from different actual charac- teristics taken from the same converter on the same channel at the same temperature, voltage and frequency conditions. resolution ethe number of input voltage levels that the converter can unambiguously distinguish be- tween. also defines the number of useful bits of infor- mation which the converter can return. sample delay ethe delay from receiving the start conversion signal to when the sample window opens. sample delay uncertainty ethe variation in the sample delay. sample time ethe time that the sample window is open. sample time uncertainty ethe variation in the sample time. sample window ebegins when the sample capac- itor is attached to a selected channel and ends when the sample capacitor is disconnected from the selected channel. successive approximation ean a/d con- version method which uses a binary search to arrive at the best digital representation of an analog input. temperature coefficients echange in the stated variable per degree centigrade temperature change. temperature coefficients are added to the typi- cal values of a specification to see the effect of tempera- ture drift. terminal based characteristic ean ac- tual characteristic which has been rotated and translat- ed to remove zero offset and full-scale error. v cc rejection eattenuation of noise on the v cc line to the a/d converter. zero offset ethe difference between the expected and actual input voltage corresponding to the first code transition. 59
80C196KB user's guide 12.0 i/o ports there are five 8-bit i/o ports on the 80C196KB. some of these ports are input only, some are output only, some are bidirectional and some have alternate func- tions. in addition to these ports, the hsi/o unit pro- vides extra i/o lines if the timer related features of these lines are not needed. port 0 is an input port which is also used as the analog input for the a/d converter. port 0 is read at location 0eh. port 1 is a quasi-bidirectional port and is read or written to through location 0fh. the three most signif- icant bits of port 1 are the control signals for the hold /hlda bus port pins. port 2 contains three types of port lines: quasi-bidirectional, input and out- put. port2 is read or written from location 10h. the ports cannot be read or written in window 15. the input and output lines are shared with other functions in the 80C196KB as shown in figure 12-1. ports 3 and 4 are open-drain bidirectional ports which share their pins with the address/data bus. on eprom and rom parts, port 3 and 4 are read and written through loca- tion 1ffeh. pin func. alternate control function reg. 2.0 output txd (serial port transmit) ioc1.5 2.1 input rxd (serial port receive) spcon.3 p2.2 input extint ioc1.1 2.3 input t2clk (timer2 clock & baud) ioc0.7 2.4 input t2rst (timer2 reset) ioc0.5 2.5 output pwm output ioc1.0 2.6 qbd * timer2 up/down select ioc2.1 2.7 qbd * timer2 capture n/a * qbd e quasi-bidirectional figure 12-1. port 2 multiple functions while discussing the characteristics of the i/o pins some approximate current or voltage specifications will be given. the exact specifications are available in the latest version of the data sheet that corresponds to the part being used. 12.1 input ports input ports and pins can only be read. there are no output drivers on these pins. the input leakage of these pins is in the microamp range. the specific values can be found in the data sheet for the device being consid- ered. figure 12-2 shows the input port structure. the high impedance input pins on the 80C196KB have an input leakage of a few microamps and are predomi- nantly capacitive loads on the order of 10 pf. in addition to acting as a digital input, each line of port 0 can be selected to be the input of the a/d converter as discussed in section 11. the capacitance on these pins is approximately 1 pf and will instantaneously in- crease by around 2 pf when the pin is being sampled by the a/d converter. port 0 pins are special in that they may individually be used as digital inputs and analog inputs at the same time. a port 0 pin being used as a digital input acts as the high impedance input ports just described. howev- er, port 0 pins being used as analog inputs are required to provide current to the internal sample capacitor when a conversion begins. this means that the input characteristics of a pin will change if a conversion is being done on that pin. in either case, if port 0 is to be used as analog or digital i/o, it will be necessary to provide power to this port through the v ref pin and angnd pins. port 0 is only sampled when the sfr is read to reduce the noise in the a/d converter. the data must be stable one state time before the sfr is read. 270651 76 note: * q1 and q2 are esd protection devices figure 12-2. input port structure 12.2 quasi-bidirectional ports port 1 and port 2 have quasi-bidirectional i/o pins. when used as inputs the data on these pins must be stable one state time prior to reading the sfr. this timing is also valid for the input-only pins of port 2 and is similar to the hsi in that the sample occurs during ph1 or during clkout low. when used as outputs, the quasi-bidirectional pins will change state shortly af- ter clkout falls. if the change was from `0' to a `1' 60
80C196KB user's guide 270651 40 chmos configuration. pfet 1 is turned on for 2 osc. periods after q makes a 0-to-1 transition. during this time, pfet 1 also turns on pfet 3 through the inverter to form a latch which holds the 1. pfet 2 is also on. figure 12-3. chmos quasi-bidirectional port circuit the low impedance pullup will remain on for one state time after the change. port 1, port 2.6 and port 2.7 are quasi-bidirectional ports. when the processor writes to the pins of a quasi- bidirectional port it actually writes into a register which in turn drives the port pin. when the processor reads these ports, it senses the status of the pin directly. if a port pin is to be used as an input then the software should write a one to its associated sfr bit, this will cause the low-impedance pull-down device to turn off and leave the pin pulled up with a relatively high im- pedance pullup device which can be easily driven down by the device driving the input. if some pins of a port are to be used as inputs and some are to be used as outputs the programmer should be careful when writing to the port. particular care should be exercised when using xor opcodes or any opcode which is a read-modify-write instruction. it is possible for a quasi-bidirectional pin to be written as a one, but read back as a zero if an external device (i.e., a transistor base) is pulling the pin below v ih . quasi-bidirectional pins can be used as input and out- put pins without the need for a data direction register. they output a strong low value and a weak high value. the weak high value can be externally pulled low pro- viding an input function. figure 12-3 shows the config- uration of a chmos quasi-bidirectional port. outputting a 0 on a quasi-bidirectional pin turns on the strong pull-down and turns off all of the pull-ups. whena1is output the pull-down is turned off and 3 pull-ups (strong-p1, weak-p3, very weak-p2) are turned on. each time a pin switches from 0 to 1 transistor p1 turns on for two oscillator periods. p2 remains on until a zero is written to the pin. p3 is used as a latch, so it is turned on whenever the pin is above the threshold value (around 2 volts). to reduce the amount of current which flows when the pin is externally pulled low, p3 is turned off when the pin voltage drops below the threshold. the current re- quired to pull the pin from a high to a low is at its maximum just prior to the pull-up turning off. an ex- ternal driver can switch these pins easily. the maxi- mum current required occurs at the threshold voltage and is approximately 700 microamps. when the port 1 pins are used as their alternate func- tions (hold , hlda , and breq ), the pins act like a standard output port. hardware connection hints when using the quasi-bidirectional ports as inputs tied to switches, series resistors may be needed if the ports will be written to internally after the part is initialized. the amount of current sourced to ground from each pin is typically 7 ma or more. therefore, if all 8 pins are tied to ground, 56 ma will be sourced. this is equivalent to instantaneously doubling the power used by the chip and may cause noise in some applications. this potential problem can be solved in hardware or software. in software, never write a zero to a pin being used as an input. in hardware, a 1k resistor in series with each pin will limit current to a reasonable value without impeding the ability to override the high impedance pullup. if all 8 pins are tied together a 120 x resistor would be rea- sonable. the problem is not quite as severe when the 61
80C196KB user's guide inputs are tied to electronic devices instead of switches, as most external pulldowns will not hold 20 ma to 0.0 volts. writing to a quasi-bidirectional port with electronic devices attached to the pins requires special attention. consider using p1.0 as an input and trying to toggle p1.1 as an output: orb ioport1, # 00000001b ; set p1.0 ; for input xorb ioport1, # 00000010b ; complement ; p1.1 the first instruction will work as expected but two problems can occur when the second instruction exe- cutes. the first is that even though p1.1 is being driven high by the 80C196KB it is possible that it is being held low externally. this typically happens when the port pin drives the base of an npn transistor which in turn drives whatever there is in the outside world which needs to be toggled. the base of the transistor will clamp the port pin to the transistor's vbe above ground, typically 0.7v. the 80C196KB will input this value as a zero even if a one has been written to the port pin. when this happens the xorb instruction will al- ways write a one to the port pin's sfr and the pin will not toggle. the second problem, which is related to the first, is that if p1.0 happens to be driven to a zero when port 1 is read by the xorb instruction, then the xorb will write a zero to p1.0 and it will no longer be useable as an input. the first situation can best be solved by the external driver design. a series resistor between the port pin and the base of the transistor often works by bringing up the voltage present on the port pin. the second case can be taken care of in the software fairly easily: ldb al, ioport1 xorb al, # 010b orb al, # 001b stb al, ioport1 a software solution to both cases is to keep a byte in ram as an image of the data to be output to the port; any time the software wants to modify the data on the port it can then modify the image byte and copy it to the port. if a switch is used on a long line connected to a quasi- bidirectional pin, a pullup resistor is recommended to reduce the possibility of noise glitches and to decrease the rise time of the line. on extremely long lines that are handling slow signals, a capacitor may be helpful in addition to the resistor to reduce noise. 12.3 output ports output pins include the bus control lines, the hso lines, and some of port 2. these pins can only be used as outputs as there are no input buffers connected to them. the output pins are output before the rising edge of ph1 and is valid some time during ph1. externally, ph1 corresponds to clkout low. it is not possible to use immediate logical instructions such as xor to tog- gle these pins. the control outputs and hso pins have output buffers with the same output characteristics as those of the bus pins. included in the category of control outputs are: txd, rxd (in mode 0), pwm, clkout, ale, bhe ,rd , and wr . the bus pins have 3 states: output high, output low, and high impedance. figure 12-4 shows the internal configuration of an output pin. 270651 77 figure 12-4. output port 62
80C196KB user's guide 12.4 ports 3 and 4/ad0 15 these pins have two functions. they are either bidirec- tional ports with open-drain outputs or system bus pins which the memory controller uses when it is ac- cessing off-chip memory. if the ea line is low, the pins always act as the system bus. otherwise they act as bus pins only during a memory access. if these pins are being used as ports and bus pins, ones must be written to them prior to bus operations. accessing port 3 and 4 as i/o is easily done from inter- nal registers. since the ld and st instructions require the use of internal registers, it may be necessary to first move the port information into an internal location be- fore utilizing the data. if the data is already internal, the ld is unnecessary. for instance, to write a word value to port 3 and 4 . . . ld intreg, portdata ; register w ; data ; not needed if ; already ; internal st intreg, 1ffeh ; register x ; port 3 and 4 to read port 3 and 4 requires that ``ones'' be written to the port registers to first setup the input port configura- tion circuit. note that the ports are reset to this input condition, but if zeroes have been written to the port, then ones must be re-written to any pins which are to be used as inputs. reading port 3 and 4 from a previ- ously written zero condition is as follows . . . ld intrega, # 0ffffh ; setup port ; change mode ; pattern st intrega, 1ffeh ; register x ; port 3 and 4 ;ld&stnot ; needed if ; previously ; written as ones ld intregb, 1ffeh ; register w ; port 3 and 4 note that while the format of the ld and st instruc- tions are similar, the source and destination directions change. when acting as the system bus the pins have strong drivers to both v cc and v ss . these drivers are used whenever data is being output on the system bus and are not used when data is being output by ports 3 and 4. the pins, external input buffers and pulldowns are shared between the bus and the ports. the ports use different output buffers which are configured as open- drain, and require external pullup resistors. (open-drain is the mos version of open-collector.) the port pins and their system bus functions are shown in figure 12-5. 270651 41 figure 12-5. port 3, 4/ad0-15 pins 63
80C196KB user's guide ports 3 and 4 on the 80C196KB are open drain ports. there is no pullup when these pins are used as i/o ports. a diagram of the output buffers connected to ports 3 and 4 and the bus pins is shown in figure 12-5. when ports 3 and 4 are to be used as inputs, or as bus pins, they must first be written with a `1'. this will put the ports in a high impedance mode. when they are used as outputs, a pullup resistor must be used external- ly. a 15k pullup resistor will source a maximum of 0.33 milliamps, so it would be a reasonable value to choose if no other circuits with pullups were connected to the pin. ports 3 and 4 are addressed as off-chip memory- mapped i/o. the port pins will change state shortly after the falling edge of clkout. when these pins are used as ports 3 and 4 they are open drains, their struc- ture is different when they are used as part of the bus. port 3 and 4 can be reconstructed as i/o ports from the address/data bus. refer to section 15.7 for details. 13.0 minimum hardware considerations the 80C196KB requires several external connections to operate correctly. power and ground must be connect- ed, a clock source must be generated, and a reset circuit must be present. we will look at each of these areas in detail. 13.1 power supply power to the 80C196KB flows through 5 pins. v cc supplies the positive voltage to the digital portion of the chip while v ref supplies the a/d converter and port0 with a positive voltage. these two pins need to be con- nected t o a 5 volt power supply. when using the a/d converter, it is desirable to connect v ref to a separate power supply, or at least a separate trace to minimize the noise in the a/d converter. the four common return pins, v ss 1, v ss 2, v ss 3, and angd, must all be nominally at 0 volts. even if the a/d converter is not being used, v ref and angd must still be connected for port0 to function. 13.2 noise protection tips due to the fast rise and fall times of high speed cmos logic, noise glitches on the power supply lines and out- puts at the chip are not uncommon. the 80C196KB is no exception to this rule. so it is extremely important to follow good design and board layout techniques to keep noise to a minimum. liberal use of decoupling caps, v cc and ground planes, and transient absorbers can all be of great help. it is much easier to design a board with these features then to search for random noise on a poorly designed pc board. for more information on noise, refer to applications note ap-125, `designing microcontroller systems for noisy environments' in the embedded control application handbook . 13.3 oscillator and internal timings on-chip oscillator the on-chip oscillator circuitry for the 80C196KB, as shown in figure 13.1, consists of a crystal-controlled, positive reactance oscillator. in this application, the crystal is operated in its fundamental response mode as an inductive reactance in parallel resonance with capac- itance external to the crystal. 270651 42 figure 13-1. on-chip oscillator circuitry the feedback resistor, rf, consists of paralleled n-chan- nel and p-channel fets controlled by the pd (power- down) bit. rf acts as an open when in powerdown mode. both xtal1 and xtal2 also have esd pro- tection on the pins which is not shown in the figure. the crystal specifications and capacitance values in figure 13-2 are not critical. 20 pf is adequate for any frequency above 1 mhz with good quality crystals. ce- ramic resonators can be used instead of a crystal in cost sensitive applications. for ceramic resonators, the man- ufacturer should be contacted for values of the capaci- tors. 64
80C196KB user's guide 270651 43 figure 13-2. external crystal connections to drive the 80C196KB with an external clock source, apply the external clock signal to xtal1 and let xtal2 float. an example of this circuit is shown in figure 13-3. the required voltage levels on xtal1 are specified in the data sheet. the signal on xtal1 must be clean with good solid levels. it is important that the minimum high and low times are met to avoid having the xtal1 pin in the tran- sition range for long periods of time. the longer the signal is in the transition region, the higher the proba- bility that an external noise glitch could be seen by the clock generator circuitry. noise glitches on the 80C196KB internal clock lines will cause unreliable op- eration. 270651 78 figure 13-3. external clock drive internal timings internal operation of the chip is based on the oscillator frequency divided by two, giving the basic time unit, known as a `state time`. with a 12 mhz crystal, a state time is 167 ns. since the 80C196KB can operate at many frequencies, the times given throughout this over- view will be in state times. two non-overlapping internal phases are created by the clock generator: phase 1 and phase 2 as shown in fig- ure 13-4. clkout is generated by the rising edge of phase 1 and phase 2. this is not the same as the 8096bh, which uses a three phase clock. changing from a three phase clock to a two phase one speeds up operation for a set oscillator frequency. consult the lat- est data sheet for ac timing specifications. 270651 44 figure 13-4. internal clock phases 13.4 reset and reset status reset starts the 80C196KB off in a known state. to reset the chip, the reset pin must be held low for at least four state times after the power supply is within tolerance and the oscillator has stabilized. as soon as the reset pin is pulled low, the i/o and control pins are asynchronously driven to their reset condition. after the reset pin is brought high, a ten state reset sequence occurs as shown in figure 13-5. during this time the ccb (chip configuration byte) is read from location 2018h and stored in the ccr (chip configu- ration register). the ea (external access) pin quali- fies whether the ccb is read from external or internal memory. figure 13-6 gives the reset status of all the pins and special function registers. 65
80C196KB user's guide figure 13-5. reset sequence 80C196KB reset sequence 270651 45 66
80C196KB user's guide watchdog timer there are three ways in which the 80C196KB can reset itself. the watchdog timer will reset the 80C196KB if it is not cleared in 64k state times. the watchdog timer is enabled the first time it is cleared. to clear the watch- dog, write a `1e` followed immediately by an `e1` to location 0ah. once enabled, the watchdog can only be disabled by a reset. rst instruction executing a rst instruction will also reset the 80C196KB. the opcode for the rst instruction is 0ffh. by putting pullups on the addr/data bus, unim- plemented areas of memory will read 0ffh and cause the 80C196KB to be reset. pin multiplexed value of the name port pins pin on reset reset mid-sized pullup ale weak pullup rd weak pullup bhe weak pullup wr weak pullup inst weak pullup ea undefined input * ready undefined input * nmi undefined input * buswidth undefined input * clkout phase 2 of clock system bus p3.0 p4.7 weak pullups ach0 7 p0.0 p0.7 undefined input * port1 p1.0 p1.7 weak pullups txd p2.0 weak pullup rxd p2.1 undefined input * extint p2.2 undefined input * t2clk p2.3 undefined input * t2rst p2.4 undefined input * pwm p2.5 weak pulldown e p2.6 p2.7 weak pullups hsi0 hsi1 undefined input * hsi2/hso4 undefined input * hsi3/hso5 undefined input * hso0 hso3 weak pulldown register name value ad e result 7ff0h hsi e status x0x0x0x0b sbuf(rx) 00h int e mask 00000000b int e pending 00000000b timer1 0000h timer2 0000h ioport1 11111111b ioport2 11000001b sp e stat/sp e con 00001011b imask1 00000000b ipend1 00000000b wsr xxxx0000b hsi e mode 11111111b ioc2 x0000000b ioc0 000000x0b ioc1 00100001b pwm e control 00h ioport3 11111111b ioport4 11111111b ios0 00000000b ios1 00000000b ios2 00000000b * these pins must be driven and not left floating. figure 13-6. chip reset status 67
80C196KB user's guide reset circuits the simplest way to reset an 80C196KB is to insert a capacitor between the reset pin and v ss . the 80C196KB has an internal pullup which has a value between 6k and 50k ohms. a 5 uf or greater capaci- tor should provide sufficient reset time as long as vcc rises quickly. figure 13-7 shows what the reset pin looks like in- ternally. the reset pin functions as an input and as an output to reset an entire system with a watchdog timer overflow, or by executing a rst instruction. for a system reset application, the reset circuit should be a one-shot with an open collector output. the reset pulse may have to be lengthened and buffered since reset is only asserted for four state times. if this is done, it is possible for the 80C196KB to start running before oth- er chips in the system are out of reset. software must take this condition into account. a capacitor cannot be connected directly to reset if it is to drive the reset pins of other chips in the circuit. the capacitor may keep the voltage on the pin from going below guaran- teed v il for circuits connected to the reset pin. fig- ure 13-8 shows an example of a system reset circuit. 13.5 minimum hardware connections figure 13-9 shows the minimum connections needed to get the 80C196KB up and running. it is important to tie all unused inputs to v cc or v ss . if these pins are 270651 46 figure 13-7. reset pin 270651 47 note: 1. the diode will provide a faster cycle time repetitive power-on-resets. figure 13-8. system reset circuit 68
80C196KB user's guide 270651 48 note: * must be driven high or low. ** v ss3 was formerly the cde pin. the cde function is no longer available. this pin must be connectd to v ss . figure 13-9. 80C196KB minimum hardware connections left floating, they can float to a mid voltage level and draw excessive current. some pins such as nmi or extint may generate spurious interrupts if left un- connected. 14.0 special modes of operation the 80C196KB has idle and powerdown modes to re- duce the amount of current consumed by the chip. the 80C196KB also has an once (on-circuit-emulation) mode to isolate itself from the rest of the components in the system. 14.1 idle mode the idle mode is entered by executing the instruction `idlpd y 1'. in the idle mode, the cpu stops execut- ing. the cpu clocks are frozen at logic state zero, but the peripheral clocks continue to be active. clkout continues to be active. power consumption in the idle mode is reduced to about 40% of the active mode. the cpu exits the idle mode by any enabled interrupt source or a hardware reset. since all of the peripherals are running, the interrupt can be generated by the hsi, hso, a/d, serial port, etc. when an interrupt brings the cpu out of the idle mode, the cpu vectors to the corresponding interrupt service routine and begins exe- cuting. the cpu returns from the interrupt service routine to the next instruction following the `idlpd y 1' instruction that put the cpu in the idle mode. in the idle mode, the system bus control pins (ale, rd ,wr , inst, and bhe ), go to their inactive states. ports 3 and 4 will retain the value present in their data latches if being used as i/o ports. if these ports are the addr/data bus, the pins will float. it is important to note the watchdog timer continues to run in the idle mode if it is enabled. so the chip must be awakened every 64k state times to clear the watchdog or the chip will reset. 14.2 powerdown mode the powerdown mode is entered by executing the in- struction, `idlpd y 2'. in the powerdown mode, all internal clocks are frozen at logic state zero and the oscillator is shut off. all 232 bytes of registers and most peripherals hold their values if v cc is maintained. power is reduced to the device leakage and is in the ua range. the 87c196kb (eprom part) will consume more power if the eprom window is not covered. 69
80C196KB user's guide 270651 49 figure 14-1. power up and power down sequence in powerdown, the bus control pins go to their inactive states. all of the output pins will assume the value in their data latches. ports 3 and 4 will continue to act as ports in the single chip mode or will float if acting as the addr/data bus. to prevent accidental entry into the powerdown mode, this feature may be disabled at reset by clearing bit 0 of the ccr (chip configuration register). since the de- fault value of the ccr bit 0 is 1, the powerdown mode is normally enabled. the powerdown mode can be exited by a chip reset or a high level on the external interrupt pin. if the reset pin is used, it must be asserted long enough for the oscillator to stabilize. when exiting powerdown with an external interrupt, a positive level on the pin mapped to int7 (either extint or port0.7) will bring the chip out of power- down mode. the interrupt does not have to be un- masked to exit powerdown. an internal timing circuit ensures that the oscillator has time to stabilize before turning on the internal clocks. figure 14-1 shows the power down and power up sequence using an external interrupt. during normal operation, before entering powerdown mode, the v pp pin will rise to v cc through an internal pullup. the user must connect a capacitor between v pp and v ss . a positive level on the external interrupt pin starts to discharge this capacitor. the internal current source that discharges the capacitor can sink approxi- mately 100 ua. when the voltage goes below about 1 volt on the v pp pin, the chip begins executing code. a 1uf capacitor would take about 4 ms to discharge to 1 volt. if the external interrupt brings the chip out of power- down, the corresponding bit will be set in the interrupt pending register. if the interrupt is unmasked, the part will immediately execute the interrupt service routine, and return to the instruction following the idlpd in- struction that put the chip into powerdown. if the in- terrupt is masked, the chip will start at the instruction following the idlpd instruction. the bit in the pend- ing register will remain set, however. all peripherals should be in an inactive state before entering powerdown. if the a/d converter is in the middle of a conversion, it is aborted. if the chip comes out of powerdown by an external interrupt, the serial port will continue where it left off. make sure that the serial port is done transmitting or receiving before en- tering powerdown. the sfrs associated with the a/d and the serial port may also contain incorrect informa- tion when returning from powerdown. when the chip is in powerdown, it is impossible for the watchdog timer to time out because its clock has stopped. systems which must use the watchdog and powerdown, should clear the watchdog right before entering powerdown. this will keep the watchdog from timing out when the oscillator is stabilizing after leaving powerdown. 14.3 once and test modes test modes can be entered on the 80C196KB by hold- ing ale, inst or rd in their active state on the rising edge of reset . the only test mode not reserved for use by intel is the once, or on-circuit-emulation mode. 70
80C196KB user's guide once is entered by driving ale high, inst low and rd low on the rising edge of reset . all pins except xtal1 and xtal2 are floated. some of the pins are not truly high impedance as they have weak pullups or pulldowns. the once mode is useful in electrically removing the 80C196KB from the rest of the system. a typical application of the once mode would be to program discrete eproms onboard without removing the 80C196KB from its socket. ale, inst, and rd are weakly pulled high or low during reset. it is important that a circuit does not in- advertantly drive these signals during reset, or a test mode could be entered by accident. 15.0 external memory interfacing 15.1 bus operation there are several different external operating modes on the 80C196KB. the standard bus mode uses a 16 bit multiplexed address/data bus. other bus modes include an 8 bit external bus mode and a mode in which the bus size can be dynamically switched between 8-bits and 16-bits. in addition, there are several options available on the type of bus control signals which make an exter- nal bus simple to design. in the standard mode, external memory is addressed through lines ad0-ad15 which form a 16 bit multi- plexed bus. the address/data bus shares pins with ports 3 and 4. figure 15-1 shows an idealized timing diagram for the external bus signals. address latch enable (ale) provides a strobe to transparent latches (74ac373s) to demultiplex the bus. to avoid confusion, the latched address signals will be called ma0-ma15 and the data signals will be named md0-md15. the data returned from external memory must be on the bus and stable for a specified setup time before the rising edge of rd (read). the rising edge of rd signals the end of the sampling window. writing to external memory is controlled with the wr (write) pin. data is valid on md0-md15 on the rising edge of wr . at this time data must be latched by the external system. the 80C196KB has ample setup and hold times for writes. when bhe is asserted, the memory connected to the high byte of the data bus is selected. when ma0 is a 0, the memory connected to the low byte of the data bus is selected. in this way accesses to a 16-bit wide memory can be to the low (even) byte only (ma0 e 0, bhe e 1), to the high (odd) byte only (ma0 e 1, bhe e 0), or the both bytes (ma0 e 0, bhe e 0). when a block of memory is decoded for reads only, the system does not have to decode bhe and ma0. the 80C196KB will discard the byte it does not need. for systems that write to external memory, a system must generate separate write strobes to both the high and low byte of memory. this is discussed in more detail later. all of the external bus signals are gated by the rising and falling edges of clkout. a zero waitstate bus cycle consists of two clkout periods. therefore, there are 4 clock edges that generate a complete bus cycle. the first falling edge of clkout asserts ale and drives an address on the bus. the rising edge of 270651 50 figure 15-1. idealized bus timings 71
80C196KB user's guide clkout drives ale inactive. the next falling edge of clkout asserts rd (read) and floats the bus for a read cycle. during a wr (write) cycle, this edge asserts wr and drives valid data on the bus. on the last rising edge of clkout, data is latched into the 80C196KB for a read cycle, or data is valid for a write cycle. ready pin the ready pin can insert wait states into the bus cycle for interfacing to slow memory or peripherals. a wait state is 2 tosc in length. since the bus is synchro- nized to clkout, it can only be held for an integral number of waitstates. because the 80C196KB is a com- pletely static part, the number of waitstates that can be inserted into a bus cycle is unbounded. refer to the next section for information on internally controlling the number of waitstates inserted into a bus cycle. there are several setup and hold times associated with the ready signal. if these timings are not met, the part may insert the incorrect number of waitstates. inst pin the inst pin is useful for decoding more than 64k of addressing space. the inst pin allows both 64k of code space and 64k of data space. for instruction fetches from external memory, the inst pin is assert- ed, or high for the entire bus cycle. for data reads and writes, the inst pin is low. the inst pin is low for the chip configuration byte fetch and for interrupt vector fetches. 15.2 chip configuration register the ccr (chip configuration register) is the first byte fetched from memory following a chip reset. the ccr is fetched from the ccb (chip configuration byte) at location 2018h in either internal or external memory depending on the state of the ea pin. the ccr is only written once during the reset sequence. once loaded, the ccr cannot be changed until the next reset. the ccr is shown in figure 15-2. the two most signif- icant bits control the level of rom/eprom protec- tion. rom/eprom protection is covered in the last section. the next two bits control the internal ready mode. the next three bits determine the bus control signals. the last bit enables or disables the powerdown mode. before the ccb fetch, if the program memory is external, the cpu assumes that the bus is configured as an 8-bit bus. in the 8-bit bus mode, during the ccb fetch, address lines 8 15 use only the weak drivers. however, in a 16-bit bus system, the external memory device will be driving the high byte of the bus while outputting the ccb. this could cause bus contention if location 2019h contains ffh. a value 20h in location 2019h will help prevent the contention. 270651 51 figure 15-2. chip configuration register ready control to simplify ready control, four modes of internal ready control are available. the modes are chosen by bits 4 and 5 of the ccr and are shown in figure 15-3. irc1 irc0 description 0 0 limit to one wait state 0 1 limit to two wait states 1 0 limit to three wait states 1 1 wait states not limited internally figure 15-3. ready control modes the internal ready control logic limits the number of waitstates that slow devices can insert into the bus cy- cle. when the ready pin is pulled low, waitstates are inserted into the bus cycle until the ready pin goes high, or the number of waitstate equal the number pro- grammed into the ccr. so the ready control is a sim- ple logical or between the ready pin and the inter- nal ready control. 72
80C196KB user's guide this feature gives very simple and flexible ready con- trol. for example, every slow memory chip select line could be ored together and connected to the ready pin with internal ready control programmed to insert the desired number of waitstates into the bus cycle. if the ready pin is pulled low during the ccr fetch, the bus controller will automatically insert 3 waitstates into the ccr bus cycle. this allows the ccr fetch to come from slow memory without having to assert the ready pin. bus control using the ccr, the 80C196KB can generate several types of control signals designed to reduce external hardware. the ale, wr , and bhe pins serve dual functions. bits 2 and 3 of the ccr specify the function performed by these control lines. standard bus control if ccr bits 2 and 3 are 1s, the standard bus control signals ale, wr , and bhe are generated as shown in figure 15-4. ale rises as the address starts to be driv- en, and falls to externally latch the address. wr is driv- en for every write. bhe and ma0 can be combined to form wrl and wrh for even and odd byte writes. 270651 52 16-bit bus cycle 270651 53 8-bit bus cycle figure 15-4. standard bus control 270651 79 figure 15-5. decoding wrl and wrh 73
80C196KB user's guide figure 15-5 is an example of external circuitry to de- code wrl and wrh . write strobe mode the write strobe mode eliminates the need to external- ly decode for odd and even byte writes. if ccr bit 2 is 0, and the bus is a 16-bit cycle, wrl and wrh are generated in place of wr and bhe . wrl is asserted for all byte writes to an even address and all word writes. wrh is asserted for all byte writes to odd ad- dresses and all word writes. the write strobe mode is shown in figure 15-6. in the eight bit mode, wrl and wrh are asserted for both even and odd addresses. address valid strobe mode address valid strobe replaces ale if ccr bit 3 is 0. when address valid strobe mode is selected, adv will be asserted after an external address is setup. it will stay asserted until the end of the bus cycle as shown in figure 15-7. adv can be used as a simple chip select for external memory. adv looks exactly like ale for back to back bus cycles. the only difference is adv will be inactive when the external bus is idle. address valid with write strobe if ccr bits 2 and 3 are 0, the address valid with write strobe mode is enabled. figure 15-8 shows the signals. 270651 55 16-bit bus cycle 270651 56 8-bit bus cycle figure 15-6. write strobe mode 270651 57 16-bit bus cycle 270651 58 8-bit bus cycle figure 15-7. address valid strobe mode 74
80C196KB user's guide 15.3 bus width the 80C196KB external bus width can be run-time configured to operate as a 16 bit multiplexed address/ data bus, or as an mcs-51 style multiplexed 16 bit ad- dress/8 bit data bus. during 16 bit bus cycles, ports 3 and 4 contain the address multiplexed with data using ale to latch the address. in 8-bit bus cycles, port 3 is multiplexed with address/data but port 4 only outputs the upper 8 ad- dress bits. the addresses on port 4 are valid through- out the entire bus cycle. figure 15-9 shows the two bus width options. 270651 59 16-bit bus cycle 270651 60 8-bit bus cycle figure 15-8. address valid with write strobe mode 270651 61 (a) 16-bit bus 270651 62 (b) 8-bit bus figure 15-9. bus width options 75
80C196KB user's guide the external bus width can be changed every bus cycle if a 1 was loaded into bit ccr.1 at reset. the bus width is changed on the fly by using the buswidth pin. if the buswidth pin is a 1, the bus cycle is 16-bits. for an 8-bit bus cycle, the buswidth pin is a zero. the buswidth is sampled by the 80C196KB after the address is on the bus. the buswidth pin has about the same timing as the ready pin. applications for the buswidth pin are numerous. for example, a system could have code fetched from 16 bit memory, while data would come from 8 bit memo- ry. this saves the cost of using two 8 bit static rams if only the capacity of one is needed. this system could be easily implemented by tying the chip select input of the 8-bit memory to the buswidth pin. if ccr bit 1 is a 0, the 80C196KB is locked into the 8 bit mode and the buswidth pin is ignored. when executing code from a 8-bit bus, some perform- ance degradation is to be expected. the prefetch queue cannot be kept full under all conditions from an 8-bit bus. also, word reads and writes to external memory will take an extra bus cycle for the extra byte. 15.4 hold /hlda protocol the 80C196KB supports a bus exchange protocol, al- lowing other devices to gain control of the bus. the protocol consists of three signals, hold , hlda , and breq . hold is an input asserted by a device which requests the 80C196KB bus. figure 15-10 shows the timing for hold /hlda . the 80C196KB responds by releasing the bus and asserting hlda . when the device is done accessing the 80C196KB memory, it re- linquishes the bus by deactivating the hold pin. the 80C196KB will remove its hdla and assume control of the bus. the third signal, breq , is asserted by the 80C196KB during the hold sequence when it has a pending external bus cycle. the 80C196KB deactivates breq at the same time it deactivates hdla . the hold , hlda , and breq pins are multiplexed with p1.7, p1.6, and p1.5, respectively. to enable hold , hlda and breq , the hlden bit (wsr.7) must be 1. hlden is cleared during reset. once this bit is set, the port1 pins cannot be returned to being quasi-bidirectional pins until the device is reset, but can still be read. the hold /hlda feature, however, can be disabled by clearing the hlden bit. the hold is sampled on phase 1, or when clkout is low. when the 80C196KB acknowledges the hold request, the output buffers for the addr/data bus, rd ,wr , bhe and inst are floated. although the strong pullup and pulldown on ale/adv are disabled, a weak pull- down is turned on. this provides the option to wire or ale with other bus masters. the request to hold laten- cy is dependent on the state of the bus controller. 270651 63 figure 15-10. hold /hlda timings 76
80C196KB user's guide maximum hold latency the time between hold being asserted and hlda being driven is known as hold latency. after recogniz- ing hold , the 80C196KB waits for any current bus cycle to finish, and then asserts hlda . there are 3 types bus cycles; 8-bit external cycle, 16-bit external cycle, and an idle bus. accessing on-chip rom/eprom is an idle bus. hold is an asynchronous input. there are two differ- ent system configurations for asserting hold . the 80C196KB will recognize hold internally on the next clock edge if the system meets thvch (hold valid to clkout high). if thvch is not met (hold applied asynchronously), hold may be recognized one clock later (see figure 15-12). consult the latest 80C196KB data sheet for the thvch specification. figure 15-12 shows the 80C196KB entering hold when the bus is idle. this is the minimum hold latency for both the synchronous and asynchronous cases. if thvch is met, hlda is asserted about on the next falling edge of clkout. see the data sheet for tclhal (clkout low to hlda low) specification. for this case, the minimum hold latency e thvcl a 0.5 states a tclhal. if hold is asserted asynchronously, the minimum hold latency increases by one state time and e thvcl a 1.5 states a tclhal. figure 15-11 summarizes the additional hold latency added to the minimum latency for the 3 types of bus cycles. when accessing external memory, add one state for each waitstate inserted into the bus cycle. for an 8-bit bus, worst case hold latency is for word reads or writes. for this case, the bus controller must access the bus twice, which increases latency by two states. for exiting hold, the minimum hold latency times ap- ply for when the 80C196KB will deassert hlda in response to hold being removed. idle bus min 16-bit external access min a 1 state 8-bit external access min a 3 states min e thvcl a 0.5 states a tclhal if thvcl is met e thvcl a 1.5 states a tclhal for asynchronous hold figure 15-11. maximum hold latency regaining bus control there is no delay from the time the 80C196KB re- moves hlda to the time it takes control of the bus. after hold is removed, the 80C196KB drops hlda in the following state and resumes control of the bus. breq is asserted when the part is in hold and needs to perform an external memory cycle. an external memo- ry cycle can be a data access or a request from the prefetch queue for a code request. a request comes from the queue when it contains two bytes or less. once asserted, it remains asserted until hold is removed. at the earliest, breq can be asserted with hlda . hold requests do not freeze the 80C196KB when exe- cuting out of internal memory. the part continues exe- cuting as long as the resources it needs are located in- ternal to the 80C196KB. as soon as the part needs to access external memory, it asserts breq and waits for the hold to be removed. at this time, the part cannot respond to any interrupt requests until hold is re- moved. when executing out of external memory during a hold , the 80C196KB keeps running until the queue is empty or it needs to perform an external data cycle. the 80C196KB cannot service any interrupts until hold is removed. the 80C196KB will also respond to hold requests in the idle mode. the latency for entering bus hold from the idle mode is the same as when executing out of internal memory. special consideration must be given to the bus arbiter design if the 80C196KB can be reset while in hold . for example, a cpu part would try and fetch the ccr from external memory after reset is brought high. now there would be two parts attempting to access 80C196KB memory. also, if another bus master is di- rectly driving ale, rd , and inst, the once mode or another test mode could be entered. the simplest solution is to make the reset pin of the 80C196KB a system reset. this way the other bus master would also be reset. examples of system reset circuits are given in section 13. 77
80C196KB user's guide case 1. meeting thvcl 270651 82 case 2. asserting hold asynchronously 270651 83 figure 15-12. hold applied asynchronously disabling hold requests clearing the hlden bit (wsr.7), can disable hold requests when consecutive memory cycles are required. clearing the hdlen bit, however, does not cause the 80C196KB to take over the bus immediately. the 80C196KB waits for the current hold request to fin- ish. then it disables the bus hold feature, causing any new requests to be ignored until the hlden bit is set again. since there is a delay from the time the code for clearing this bit is fetched to the time it is actually exe- cuted, the code that clears hlden needs to be a few instructions ahead of the block that needs to be protect- ed from hold requests. the safest way is to add a jbc instruction to check the status of the hlda pin after the code that clears the hlden bit. figure 15-13 is an example of code that prevents the part from executing a new instruction until both current hold requests are serviced and the hold feature is disabled. 15.5 ac timing explanations figure 15-14 shows the timing of the addr/data bus and control signals. refer to the latest data sheet for the ac timings to make sure your system meets specifications. the major timing specifications are ex- plained in figure 15-15. di ; disable interrupts andb wsr, # oefh ; disable hold request wait: jbc port1, 6, wait; check the hlda pin # ; if set, execute # ; protected instructions # orb wsr, # 80h ; enable hold requests ei ; enable interrupts note: interrupts should be disabled to prevent code interruption figure 15-13. hold code 78
80C196KB user's guide 270651 80 figure 15-14. ac timing diagrams 79
80C196KB user's guide 270651 81 270651 84 figure 15-14. ac timing diagrams (continued) 80
80C196KB user's guide timings the memory system must meet: t avyv e address valid to ready setup: maximum time the memory system has to decode ready after address is output by the 80C196KB to guarantee at least one-wait state will occur. t llyv e ale low to ready setup: maximum time the memory system has to decode ready after ale falls to guarantee at least one wait state will occur. t ylyh e ready low to ready high: maxi- mum amount of nonready time or the maximum number of wait states that can be inserted into a bus cycle. since the 80C196KB is a completely static part, t ylyh is unbounded. t clyx e ready hold after clkout low: minimum time the level on the ready pin must be valid after clkout falls. the minimum hold time is always 0 ns. if maximum value is exceeded, addition- al wait states will occur. t llyx e ready hold after ale low: mini- mum time the level on the ready pin must be valid after ale falls. if maxi- mum value is exceeded, additional wait states will occur. t avgv e address valid to buswidth val- id: maximum time the memory system has to decode buswidth after ad- dress is output by the 80C196KB. if exceeded, it is not guaranteed the 80C196KB will respond with an 8- or 16-bit bus cycle. t llgv e ale low to buswidth valid: maxi- mum time after ale/adv falls until buswidth must be valid. if exceeded, it is not guaranteed the 80C196KB will respond with an 8- or 16-bit bus cycle. t clgx e buswidth hold after clkout low: minimum time buswidth must be held valid after clkout falls. al- ways 0 ns of the 80C196KB. t avdv e address valid to input data valid: maximum time the memory system has to output valid data after the 80C196KB outputs a valid address. t rldv e rd low to input data valid: maximum time the memory system has to output valid data after the 80C196KB asserts rd . t cldv e clkout low to input data valid: maximum time the memory system has to output valid data after the clkout falls. t rhdz e rd high to input data float: time af- ter rd is inactive until the memory sys- tem must float the bus. if this timing is not met, bus contention will occur. t rxdx e data hold after rd inactive: time after rd is inactive that the memory system must hold data on the bus. always 0 ns on the 80C196KB. timings the 80C196KB will provide: f xtal e frequency on xtal1: frequency of sig- nal input into the 80C196KB. the 80C196KB runs internally at (/2 f xtal . t osc e 1/f xtal : all a.c. timings are refer- enced to t osc . t xhch e xtal1 high to clkout high or low: needed in systems where the sig- nal driving xtal1 is also a clock for external devices. t clcl e clkout cycle time: nominally 2 t osc . t chcl e clkout high period: needed in sys- tems which use clkout as clock for external devices. t cllh e clkout falling edge to ale/adv rising: a help in deriving other timings. t llch e ale/adv falling edge to clkout rising: a help in deriving other timings. t lhlh e ale cycle time: time between ale pulses. t lhll e ale/adv high period: useful in de- termining ale/adv rising edge to address valid. external latches must also meet this spec. t avll e address setup to ale/adv falling edge: length of time address is val- id before ale/adv falls. external latches must meet this spec. t llax e address hold after ale/adv fall- ing edge: length of time address is valid after ale/adv falls. external latches must meet this spec. t llrl e ale/adv low to rd low: length of time after ale/adv falls before rd is asserted. could be needed to insure proper memory decoding takes place be- fore a device is enabled. figure 15-15. ac timing explanations 81
80C196KB user's guide t rlcl e rd low to clkout falling edge: length of time from rd asserted to clkout falling edge: useful for sys- tems based on clkout. t rlrh e rd low to rd high: rd pulse width. t rhlh e rd high to ale/adv asserted: time between rd going inactive and next ale/adv , also used to calculate time between inactive and next address valid. t rlaz e rd low to address float: used to calculate when the 80C196KB stops driving address on the bus. t llwl e ale/adv low edge to wr low: length of time ale/adv falls before wr is asserted. could be needed to en- sure proper memory decoding takes place before a device is enabled. t clwl e clkout falling edge to wr low: time between clkout going low and wr being asserted. useful in systems based on clkout. t qvwh e data valid to wr rising edge: time between data being valid on the bus and wr going inactive. memory devices must meet this spec. t chwh e clkout high to wr rising edge: time between clkout going high and wr going inactive. useful in systems based on clkout. t wlwh e wr low to wr high: wr pulse width. memory devices must meet this spec. t whqx e data hold after wr rising edge: amount of time data is valid on the bus after wr going inactive. memory devic- es must meet this spec. t whlh e wr rising edge to ale/adv rising edge: time between wr going inactive and next ale/adv . also used to cal- culate wr inactive and next address valid. t whbx e bhe , inst, hold after wr rising edge: minimum time these signals will be valid after wr inactive. t rhbx e bhe , inst hold after rd rising edge: minimum time these signals will be valid after rd inactive. t whax e ad8 15 hold after wr rising edge: minimum time the high byte of the ad- dress in 8-bit mode will be valid after wr inactive. t rhax e ad8 15 hold after rd rising edge: minimum time the high byte of the ad- dress in 8-bit mode will be valid after rd inactive. figure 15-15. ac timing explanations (continued) 270651 66 figure 15-16. 8-bit system with eprom 82
80C196KB user's guide 15.6 memory system examples external memory systems for the 80C196KB can be set up in many different ways. figure 15-16 shows a simple 8 bit system with a single eprom. the adv mode can be selected to provide a chip select to the memory. by setting bit ccr.1 to 0, the system is locked into the eight bit mode. an eight bit system with eprom and ram is shown in figure 15-17. the eprom is decod- ed in the lower half of memory,and the ram in the upper half. figure 15-18 shows a 16 bit system with 2 eproms. again, adv is used to chip select the memory. figure 15-19 shows a system with dynamic bus width. code is executed from the two eproms and data is stored in the single ram. note the chip select of the ram also is input to the buswidth pin to select an eight bit cycle. 270651 67 figure 15-17. 8-bit system with eprom and ram 270651 68 figure 15-18. 16-bit system with eprom 83
80C196KB user's guide 270651 69 figure 15-19. 16-bit system with dynamic buswidth 270651 70 figure 15-20. i/o port reconstruction 84
80C196KB user's guide 15.7 i/o port reconstruction when a single-chip system is being designed using a multiple chip system as a prototype, it may be neces- sary to reconstruct i/o ports 3 and 4 using a memory mapped i/o technique. the circuit to reconstruct the ports is shown in figure 15-20. it can be attached to a 80C196KB system which has the required address de- coding and bus demultiplexing. the output circuitry is a latch that operates when 1ffeh or 1fffh are placed on the ma lines. the inverters surrounding the latch create an open-collector output to emulate the open-drain output found on the 80C196KB. the reset line sets the ports to all 1s when the chip is reset. the voltage and current specifi- cations of the port will be different from the 80C196KB, but the functionality will be the same. the input circuitry is a bus transceiver that is addressed at 1ffeh and 1fffh. if the ports are going to be either inputs or outputs, but not both, some of the cir- cuitry may be eliminated. 16.0 using the eprom the 87c196kb contains 8 kbytes of ultraviolet eras- able and electrically programmable read only memo- ry (eprom). when ea is a ttl high, the eprom is located at memory locations 2000h through 3fffh. applying a 12.75v to ea when the chip is reset places the 87c196kb device in the eprom programming mode. the programming mode supports eprom pro- gramming and verification. the following is a brief de- scription of each of the programming modes: the auto configuration byte programming mode programs the programming chip configuration byte and the chip configuration byte. the auto programming mode enables an 87c196kb to program itself without using an eprom programmer. the slave programming mode provides a standard interface for programming any number of 87c196kb's by a master device such as an eprom programmer. the run-time programming mode allows individu- al eprom locations to be programmed at run-time under complete software control. (run-time pro- gramming is done with ea e 5v.) in the programming mode some i/o pins have new functions. these pins determine the programming func- tion, provide programming control signals and slave id numbers, and pass error information. figure 16-1 shows how the pins are renamed. figure 16-2 describes each new pin function. pmode selects the programming mode (see figure 16-3). the 87c196kb does not need to be in the pro- gramming mode to do run-time programming; it can be done at any time. when an 87c196kb eprom device is not being erased the window must be covered with an opaque label. this prevents functional degradation and data loss from the array. 16.1 power-up and power-down to avoid damaging devices during programming, fol- low these rules: rule y 1v pp must be within 1v of v cc while v cc is below 4.5v. rule y 2v pp can not be higher than 5.0v until v cc is above 4.5v. rule y 3v pp must not have a low impedance path to ground when v cc is above 4.5v. rule y 4ea must be brought to 12.75v before v pp is brought to 12.75v (not needed for run- time programming). rule y 5 the pmode and sid pins must be in their desired state before reset rises. rule y 6 all voltages must be within tolerance and the oscillator stable before reset rises. rule y 7 the supplies to v cc ,v pp ,ea and re- set must be well regulated and free of spikes and glitches. to adhere to these rules you can use the following pow- er-up and power-down sequences: 85
80C196KB user's guide power-up reset e 0v v cc e v pp e ea e 5v clock on (if using an external clock instead of the internal oscillator) pale e prog e port3, 4 e v ih (1) sid and pmode valid ea e 12.75v (2) v pp e 12.75v (3) wait (wait for supplies and clock to settle) reset e 5v wait tshll (reset high to first pale low) begin power-down reset e 0v v pp e 5v ea e 5v pale e prog e sid e pmode e port3, 4 e 0v v cc e v pp e ea e 0v clock off notes: 1. v ih e logical ``1'' (2.4v minimum) 2. the same power supply can be used for ea and v pp . however, the ea pin must be powered up before v pp is powered up. also, ea should be protected from noise to prevent damage to it. 3. exceeding the maximum limit on v pp for any amount of time could damage the device permanently. the v pp source must be well regulated and free of glitches. 16.2 reserved locations all intel reserved locations except address 2019h, when mapped internally or externally, must be loaded with 0ffh to ensure compatibility with future devices. address 2019h must be loaded with 20h. 270651 71 figure 16-1. programming mode pin functions 86
80C196KB user's guide mode name function general pmode (p0 0.4, 0.5, 0.6, 0.7) programming mode select. determines the eprom programming algorithm that is performed. pmode is sampled after a chip reset and should be static while the part is operating. auto pccb pver program verification output. a high signal indicates that the bytes have programmed correctly. programming mode (p2.0) pale programming ale input. indicates that port3 contains the data to be programmed into the ccb and the pccb. (p2.1) mode auto programming (p2.7) pact programming active output. indicates when programming activity is complete. pval (p3.0) program valid output. indicates the success or failure of programming. a zero indicates successful programming. 3 and 4 ports address/command/data bus. used in the auto programming mode as a regular system bus to access external memory. should have pullups to v cc (15 k x ). mode slave programming 0.1, 0.2, 0.3) (hsi 0.0, sid slave id number. used to assign a pin of port 3 or 4 to each slave to use for passing programming verification acknowledgement. for example, if gang programming in the slave programming mode, the slave with sid e 001 will use port 3.1 to signal correct or incorrect program verification. (p2.1) pale programming ale input. indicates that ports 3 and 4 contain a command/address. (p2.2) prog programming input. falling edge indicates valid data on pbus and the beginning of programming. rising edge indicates end of programming. (p2.0) pver program verification output. low signal after rising edge of prog indicates programming was not successful. (p2.4) ainc auto increment input. active low input signal indicates that the auto increment mode is enabled. auto increment will allow reading or writing of sequential eprom locations without address transactions across the pbus for each read or write. ports address/command/data bus. used to pass commands, addresses, and data to and from 87c196kbs in the slave programming mode. 3 and 4 one pin each can be assigned to up to 15 slaves to pass verification information. figure 16-2. programming mode pin definitions pmode programming mode 0 4 reserved 5 slave programming 6 rom dump 7 0bh reserved 0ch auto programming 0dh program configuration byte 0eh 0fh reserved figure 16-3. programming function pmode values 16.3 programming pulse width register (ppw) in the auto and run-time programming modes the width of the programming pulse is determined by the 8 bit ppw (programming pulse width) register. in the auto programming mode, the ppw is loaded from lo- cation 4014h in external memory. in run-time pro- gramming mode, the ppw is located in window 14 at 04h. in order for the eprom to properly program, the pulse width must be set to approximately 100 us. the pulse width is dependent on the oscillator frequen- cy and is calculated with the following formula: pulse width e ppw * (tosc * 8) ppw e 150 @ 12 mhz in the slave programming mode the width of the pro- gramming pulse is determined by the prog signal. 87
80C196KB user's guide 16.4 auto configuration byte programming mode the programming chip configuration byte (pccb) is a non-memory mapped eprom location. it gets load- ed into the ccr during reset for auto and slave pro- gramming. the auto configuration byte programming mode programs the pccb. the chip configuration byte (ccb) is at location 2018h and can be programmed like any other eprom location using auto, slave, or run-time programming. however, you can also use auto configuration byte programming to program the ccb when no other loca- tions need to be programmed. the ccb is programmed with the same value as the pccb. the auto configuration byte programming mode is entered by following the power-up sequence described in section 16.1 with pmode e 0dh, port 4 e 0ffh, and port 3 e the data to be programmed into the pccb and ccb. when a 0 is placed on pale the ccb and pccb are automatically programmed with the data on port 3. after programming, pver is driv- en high if the bytes programmed correctly and low if they did not. once the pccb and ccb are programmed, all pro- gramming activities and bus operations use the selected bus width, ready control, bus controls, and read/ write protection until you erase the device. you must be careful when programming the read and write lock bits in the pccb and ccb. if the read 270651 73 notes: tie port 3 to the value desired to be programmed into ccb and pccb. make all necessary minimum connections for power, ground and clock. figure 16-5. the pccb programming mode or write lock bits are enabled, some programming modes will require security key verification before exe- cuting and some modes will not execute. see figure 16-10 and the sections on each programming mode for details of the effects of enabling the lock bits. if the pccb is not programmed, the ccr will be load- ed with 0fffh when the device is in the programming mode. 16.5 auto programming mode the auto programming mode provides the ability to program the 87c196kb eprom without using an eprom programmer. for this mode follow the power- up sequence described in section 16.1 with pmode e 0ch. external location 4014h must contain the ppw. when reset rises, the 87c196kb automatically pro- grams itself with the data found at external locations 4000h through 5fffh. the 87c196kb begins programming by setting pact low. then it reads a word from external memory. the modified quick-pulse programming algorithm (de- scribed later) programs the corresponding eprom lo- cation. since the erased state of a byte is 0ffh, the auto programming mode will skip locations with 0ffh for data. when all 8k have been programmed, pact goes high and the device output sa0on pval (p3.0) if it programmed correctly and a 1 if it failed. figure 16-4 shows a minimum configuration using an 8k c 8 eprom to program an 87c196kb in the auto programming mode. auto programming mode and the ccb/pccb in the auto programming mode the ccr is loaded with the pccb. the pccb must correspond to the memory system of the programming setup, including the ready and bus control selections. you can pro- gram the pccb using the auto configuration byte programming mode (see section 16.4). the data in the pccb takes effect upon reset. if you enable the read and write lock bits during auto programming but do not reset the device, auto pro- gramming will continue. if you enable either the read or write lock bits in the ccb using auto configuration byte programming and then reset the 87c196kb for auto programming, the device does a security key verification. the same security keys that reside at internal addresses 2020h 202fh must reside at external locations 4020h 402fh. if the keys match, auto programming continues. if the keys do not match, the device enters an endless loop of internal execution. 88
80C196KB user's guide 270651 72 notes: * inputs must be driven high or low. ** allow reset to rise after the voltages to v cc ,ea , and v pp are stable. figure 16-4. auto programming mode 89
80C196KB user's guide 16.6 slave programming mode any number of 87c196kbs can be programmed by a master programmer through the slave programming mode. there is no 87c196kb dependent limit to the number of devices that can be programmed. in this mode, the 87c196kb programs like a simple eprom device and responds to three different com- mands: data program, data verify, and word dump. the 87c196kb uses ports 3 and 4 and five other pins to select commands, to transfer data and addresses, and to provide handshaking. the two most significant bits on ports 3 and 4 specify the command and the lower 14 bits contain the address. the address ranges from 2000h-3fffh and refers to internal memory space. figure 16-6 is a list of valid programming commands. p4.7 p4.6 action 0 0 word dump 0 1 data verify 1 0 data program 1 1 reserved figure 16-6. slave programming mode commands the 87c196kb receives an input signal, pale ,toin- dicate a valid command is present. prog causes the 87c196kb to read in or output a data word. pver indicates if the programming was successful. ainc au- tomatically increments the address for the data pro- gram and word dump commands. data program command a data program command is illustrated in figure 16- 7. asserting pale latches the command and address on ports 3 and 4. prog is asserted to latch the data present on ports 3 and 4. prog also starts the actual programming sequence. the width of the prog pulse determines the programming pulse width. note that the ppw is not used in the slave programming mode. after the rising edge of prog , the slaves automatically verify the contents of the location just programmed. pver is asserted if the location programmed correctly. this gives verification information to programmers which can not use the data verify command. the ainc pin can increment to the next location or a new data program command can be issued. 270651 74 figure 16-7. data program command in slave mode 90
80C196KB user's guide pver is a 1 if the data program was successful. pver isa0ifthe data program was unsuccessful. figure 16-7 shows the relationship of pale , prog , and pver to the command/data path on ports 3 and 4 for the data program command. data verify command when the data verify command is sent, the slaves in- dicate correct or incorrect verification of the previous data program command by driving one bit of ports 3 and 4. a 1 indicates a correct verification, and a 0 indi- cates incorrect verification. the sid (slave i.d) of each slave determines which bit of ports 3 and 4 will be driven. for example, a sid of 0001 would drive port 3.1. prog governs when the slaves drive the bus. fig- ure 16-8 shows the relationship of ports 3 and 4 to pale and prog . a data verify command is always preceded by a data program command in a programming system with as many as 16 slaves. however, a data verify command does not have to follow every data program com- mand. word dump command when the word dump command is issued, the 87c196kb adds 2000h to the address field of the com- mand and places the value at the new address on ports 3 and 4. for example, when the slave receives the com- mand 0100h, it will place the word at internal address 2100h on ports 3 and 4. prog governs when the slave drives the bus. the timings are the same as shown in figure 16-7. note that the word dump command only works when a single slave is attached to the bus. also, there is no restriction on commands that precede or follow a word dump command. gang programming with the slave programming mode gang programming of 87c196kbs can be done using the slave programming mode. there is no 87c196kb based limit on the number of devices that may be hooked to the same port 3 and 4 data path for gang programming. if more than 16 devices are being gang programmed, the pver outputs of each chip can be used for verifica- tion. the master programmer can issue a data pro- gram command, then either watch every device's error signal, or and all the signals together to form a sys- tem pver. 270651 75 figure 16-8. ports 3 and 4 to pale and prog 91
80C196KB user's guide if 16 or fewer 87c196kbs are to be gang programmed at once, a more flexible form of verification is available by giving each device a unique sid. the master pro- grammer can issue a data verify command after the data program command. when a verify command is seen by the slaves, each will drive a bit of ports 3 or 4 corresponding to its unique sid . a 1 indicates the ad- dress verified, whil e a 0 means it failed. slave programming mode and the ccb/pccb devices in the slave programming mode use ports 3 and 4 as the command/data path. the data bus is not used. therefore, you do not need to program either the ccb or the pccb before starting slave programming. you can program the ccb like any other location in slave mode. data programmed into the ccb takes ef- fect upon reset. if you enable either the read or the write lock bits in the ccb during slave program- ming and do not reset the device, slave programming will continue. if you do reset the device, the device first does a security key verification. the same security keys that reside at internal addresses 2020h 202fh must reside at external addresses 4020h 402fh. if the keys match, slave programming continues. if the keys do not match, the device enters an endless loop of internal exe- cution. 16.7 run-time programming the 87c196kb can program itself under software con- trol. one byte or word can be programmed instead of the entire array. the only additional requirement is that you apply a programming voltage to v pp and have the ambient temperature at 25 c. run-time program- ming is done with ea at a ttl high (internal memory enabled). to run-time program, the user writes to the location to be programmed. the value of the ppw register de- termines the programming pulse. to ensure 87c196kc compatibility, the idle mode should be used for run- time programming. figure 16-9 is the recommended code sequence for run-time programming. the modi- fied quick pulse algorithm guarantees the programmed eprom cell for the life of the part. run-time programming and the ccb/pccb for run-time programming, the ccr is loaded with the ccb. run-time programming is done with ea equal to a ttl-high (internal execution) so the internal ccb must correspond to the memory system of the applica- tion setup. you can use auto configuration byte pro- gramming or a generic programmer to program the ccb before using run-time programming. ld wsr, # 14 ;initialize programmable ld ppw, # value ;pulse width program: pop address temp ;load program data pop data temp ;and address pushf ld count, # 25t loop: st data temp, [ addr temp ] ;begin programming ;enter idle mode djnz count, l00p ;loop 25 times popf ret note: * not really needed on current 87c196kb part figure 16-9. future run-time programming algorithm 92
80C196KB user's guide the ccb can also be programmed during run-time programming like any other eprom location. data programmed into the ccb takes effect immedi- ately. if the write lock bit of the ccb is enabled, the array can no longer be programmed. you should only program the write lock bit when no further pro- gramming will be done to the array. if the read lock bit is programmed the array can still be programmed using run-time programming but a data access will only be performed when the program counter is between 2000h and 3fffh. 16.8 rom/eprom memory protection options write protection is available for eprom parts, and read protection is provided for both rom and eprom parts. write protection is enabled by clearing the loc0 bit in the ccr. when write protection is enabled, the bus controller will cycle through the write sequence but will not actually drive data to the eprom or enable v pp to the eprom. this protects the entire eprom (loca- tions 2000h 3fffh) from inadvertent or unautho- rized programming. read protection is enabled by clearing the loc1 bit of the ccr. when read protection is selected, the bus controller will only perform a data read from the ad- dress range 2020h-202fh (security key) and 2040h- 3fffh if the slave program counter is in the range 2000h-3fffh. since the slave pc can be as many as 4 bytes ahead of the cpu program counter, an instruc- tion after address 3ffah may not access protected memory. also note the interrupt vectors and ccb are not read protected. ea is latched on reset so the device cannot be switched from internal to external memory by toggling ea . if the ccr has any protection enabled, the security key is write protected to keep unauthorized users from ov- erwriting the key with a known security key. note: substantial effort has been made to provide an excel- lent program protection scheme. however, intel can- not and does not guarantee that these protection methods will always prevent unauthorized access. ccb.1 ccb.0 rd wr protection lock lock 1 1 array is unprotected. rom dump mode and all programming modes are allowed. 0 1 array is read protected. run- time programming is allowed. auto, slave, and rom dump mode are allowed after security key verification. 1 0 array is write protected. auto, slave, and rom dump mode are allowed after security key verification. run-time programming is not allowed. 0 0 array is read and write protected. auto, slave, and rom dump mode are allowed after security key verification. run-time programming is not allowed. figure 16-10 rom dump mode you can use the security key and rom dump mode to dump the internal rom/eprom for testing purposes. the security key is a 16 byte number. the internal rom/eprom must contain the security key at loca- tions 2020h 202fh. the user must place the same security key at external address 4020h 402fh. before doing a rom dump, the device checks that the keys match. 93
80C196KB user's guide for the 87c196kb, the rom dump mode is entered like the other programming modes described in section 16.1 with pmode equal to 6h. for the 83c196kb, the rom dump mode is entered by placing ea at a ttl high, holding ale low and holding inst and rd high on the rising edge of reset. the device first verifies the security key. if the security keys do not match, the device puts itself into an endless loop of internal execution. if the keys match, the device dumps internal locations 2000h-3fffh to external locations 4000h 5fffh. 16.9 algorithms the modified quick-pulse algorithm the modified quick-pulse algorithm must be used to guarantee programming over the life of the eprom in run-time and slave programming modes. the modified quick-pulse algorithm calls for each eprom location to receive 25 separate 100 us ( g 5 m s) programming cycles. verification is done after the 25th pulse. if the location verifies, the next location is programmed. if the location fails to verify, the location fails the programming sequence. once all locations are programmed and verified, the entire eprom is again verified. programming of 87c196kb eproms is done with v pp e 12.75v g 0.25v and v cc e 5.0v g 0.5v. signature word the 87c196kb contains a signature word at location 2070h. the word can be accessed in the slave mode by executing a word dump command. the programming voltages are determined by reading the test rom at locations 2072h and 2073h. the voltages are calculat- ed by using the following equation. voltage e 20/256 * (test rom data) the values for the signature word and voltage levels are shown in figure 16-10. description location value signature word 2070h 897ch programming v cc 2072h 040h (5.0v) programming v pp 2073h 0a3h (12.75v) figure 16-10. signature word and voltage levels erasing the 87c196kb after each erasure, all bits of the 87c196kb are logical 1s. data is introduced by selectively programming 0s. the only way to chang ea0toa1isby exposure to ultraviolet light. erasing begins upon exposure to light with wavelengths shorter than approximately 4000 angstroms. it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000 angstrom range. constant exposure to room level fluorescent lighting could erase an 87c196kb in about 3 years. it would take about 1 week in direct sunlight to erase an 87c196kb. opaque labels should always be placed over the win- dow to prevent unintentional erasure. in the power- down mode, the part will draw more current than nor- mal if the eprom window is exposed to light. the recommended erasure procedure for the 87c196kb is exposure to ultraviolet light which has a wavelength of 2537 angstroms. the integrated dose (uv intensity * exposure time) should be a minimum of 15 wsec/cm 2 . the total time for erasure is about 15 to 20 minutes at this level of exposure. the 87c196kb should be placed within 1 inch of the lamp during expo- sure. the maximum integrated dose an 87c196kb can be exposed to without damage is 7258 wsec/cm 2 (1 week @ 12000 uw/cm 2 ). exposure to uv light greater than this can cause permanent damage. 94

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